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add isntance naming templates

This commit is contained in:
Jesse Cirimelli-Low 2023-08-03 16:24:24 -07:00
parent 5e01bad2ee
commit 1aa04db2b6
5 changed files with 15 additions and 9 deletions
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4
compiler/characterizer/simulation.py
View File

@ -619,6 +619,10 @@ class simulation():
bl_names = []
exclude_set = self.get_bl_name_search_exclusions()
print(paths)
print(cell_bl)
print(cell_mod)
print(exclude_set)
for int_net in [cell_bl, cell_br]:
bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
if OPTS.use_pex and OPTS.pex_exe[0] != "calibre":

8
compiler/modules/bitcell_array.py
View File

@ -64,12 +64,12 @@ class bitcell_array(bitcell_base_array):
core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
core_block[1][0] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size,name_template="bit_r{0}_c{1}")
self.pattern.connect_array()
for key in self.cell_inst.keys():
if key != (0,0):
self.trim_insts.add(self.cell_inst[key].name)
#for key in self.cell_inst.keys():
# if key != (0,0):
# self.trim_insts.add(self.cell_inst[key].name)
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""

6
compiler/modules/dummy_array.py
View File

@ -53,11 +53,11 @@ class dummy_array(bitcell_base_array):
""" Create the module instances used in this design """
self.cell_inst={}
core_block = [[0 for x in range(1)] for y in range(2)]
core_block[0][(0+self.mirror) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[0][(1+self.mirror) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size, name_template="bit_r{0}_c{1}")
self.pattern.connect_array()

4
compiler/modules/pattern.py
View File

@ -23,6 +23,7 @@ class pattern():
core_block:block,
num_rows:int,
num_cols:int,
name_template,
num_cores_x: Optional[int] = 0,
num_cores_y: Optional[int] = 0,
cores_per_x_block: int = 1,
@ -50,6 +51,7 @@ class pattern():
self.core_block = core_block
self.num_rows = num_rows
self.num_cols = num_cols
self.name_template = name_template
self.num_cores_x = num_cores_x
self.num_cores_y = num_cores_y
if num_cores_x == 0:
@ -122,7 +124,7 @@ class pattern():
if(inst.is_bitcell):
self.bit_rows[col+dc] += 1
self.bit_cols[row+dr] += 1
self.parent_design.cell_inst[row + dr, col + dc] = self.parent_design.add_existing_inst(inst,"bit_r{}_c{}".format(row +dr, col+dc))
self.parent_design.cell_inst[row + dr, col + dc] = self.parent_design.add_existing_inst(inst,self.name_template.format(row +dr, col+dc))
self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(row+dr, col+dc))
def connect_array(self) -> None:

2
compiler/modules/replica_column.py
View File

@ -105,7 +105,7 @@ class replica_column(bitcell_base_array):
else:
core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
current_row += 1
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size)
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size, name_template="rbc_r{0}_c{1}")
self.pattern.connect_array()
def add_layout_pins(self):