mirror of https://github.com/VLSIDA/OpenRAM.git
Simplify closest edge calculation in signal escape router
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@ -76,6 +76,27 @@ class signal_escape_router(router):
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self.replace_layout_pins()
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def get_closest_edge(self, point):
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""" Return a point's the closest edge and the edge's axis direction. """
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ll, ur = self.bbox
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# Snap the pin to the perimeter and break the iteration
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ll_diff_x = abs(point.x - ll.x)
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ll_diff_y = abs(point.y - ll.y)
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ur_diff_x = abs(point.x - ur.x)
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ur_diff_y = abs(point.y - ur.y)
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min_diff = min(ll_diff_x, ll_diff_y, ur_diff_x, ur_diff_y)
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if min_diff == ll_diff_x:
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return "left", True
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if min_diff == ll_diff_y:
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return "bottom", False
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if min_diff == ur_diff_x:
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return "right", True
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return "top", False
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def prepare_path(self, path):
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"""
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Override the `prepare_path` method from the `router` class to prevent
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@ -88,28 +109,20 @@ class signal_escape_router(router):
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for i in range(len(nodes)):
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node = nodes[i]
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c = node.center
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# Haven't overflown yet
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if ll.x < c.x and c.x < ur.x and ll.y < c.y and c.y < ur.y:
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new_nodes.append(node)
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continue
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# Snap the pin to the perimeter and break the iteration
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ll_diff_x = abs(c.x - ll.x)
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ll_diff_y = abs(c.y - ll.y)
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ur_diff_x = abs(c.x - ur.x)
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ur_diff_y = abs(c.y - ur.y)
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min_diff = min(ll_diff_x, ll_diff_y, ur_diff_x, ur_diff_y)
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if min_diff == ll_diff_x:
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edge, _ = self.get_closest_edge(c)
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if edge == "left":
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fake_center = vector3d(ll.x + self.half_wire, c.y, c.z)
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if min_diff == ll_diff_y:
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if edge == "bottom":
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fake_center = vector3d(c.x, ll.y + self.half_wire, c.z)
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if min_diff == ur_diff_x:
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if edge == "right":
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fake_center = vector3d(ur.x - self.half_wire, c.y, c.z)
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if min_diff == ur_diff_y:
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if edge == "top":
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fake_center = vector3d(c.x, ur.y - self.half_wire, c.z)
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node.center = fake_center
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new_nodes.append(node)
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break
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@ -168,26 +181,18 @@ class signal_escape_router(router):
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c = pin.center()
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# Find the closest edge
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ll_diff_x = abs(c.x - ll.x)
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ll_diff_y = abs(c.y - ll.y)
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ur_diff_x = abs(c.x - ur.x)
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ur_diff_y = abs(c.y - ur.y)
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min_diff = min(ll_diff_x, ll_diff_y, ur_diff_x, ur_diff_y)
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edge, vertical = self.get_closest_edge(c)
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# Keep the fake pin out of the SRAM layout are so that they won't be
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# blocked by previous signals if they're on the same orthogonal line
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if min_diff == ll_diff_x:
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if edge == "left":
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fake_center = vector(ll.x - self.track_wire * 2, c.y)
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vertical = True
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if min_diff == ll_diff_y:
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if edge == "bottom":
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fake_center = vector(c.x, ll.y - self.track_wire * 2)
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vertical = False
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if min_diff == ur_diff_x:
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if edge == "right":
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fake_center = vector(ur.x + self.track_wire * 2, c.y)
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vertical = True
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if min_diff == ur_diff_y:
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if edge == "top":
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fake_center = vector(c.x, ur.y + self.track_wire * 2)
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vertical = False
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# Create the fake pin shape
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layer = self.get_layer(int(not vertical))
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