mirror of https://github.com/VLSIDA/OpenRAM.git
power ring working
This commit is contained in:
Jesse Cirimelli-Low
parent
8794070ebc
commit
8f2e4c6914
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@ -2157,6 +2157,13 @@ class layout():
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# Add the gnd ring
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self.add_ring([ll, ur])
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def reset_coordinates(self):
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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self.translate_all(ll)
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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def add_ring(self, bbox=None, width_mult=8, offset=0):
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"""
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Add a ring around the bbox
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@ -2209,7 +2216,7 @@ class layout():
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size=(supply_vias,
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supply_vias))
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def add_power_ring(self):
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def add_power_ring(self, h_layer="m2", v_layer="m1"):
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"""
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Create vdd and gnd power rings around an area of the bounding box
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argument. Must have a supply_rail_width and supply_rail_pitch
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@ -2217,42 +2224,42 @@ class layout():
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left/right/top/bottom vdd/gnd center offsets for use in other
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modules..
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"""
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[ll, ur] = self.bbox
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supply_rail_spacing = self.supply_rail_pitch - self.supply_rail_width
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supply_rail_spacing = self.supply_rail_pitch
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height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing
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width = (ur.x - ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing
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# LEFT vertical rails
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offset = ll + vector(-2 * self.supply_rail_pitch,
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-2 * self.supply_rail_pitch)
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left_gnd_pin = self.add_layout_pin(text="gnd",
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layer="m2",
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offset = ll + vector(-2*self.supply_rail_pitch,
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-2*self.supply_rail_pitch)
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self.left_gnd_pin = self.add_layout_pin(text="gnd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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height=height + 2 * supply_rail_spacing)
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offset = ll + vector(-1 * self.supply_rail_pitch,
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-1 * self.supply_rail_pitch)
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left_vdd_pin = self.add_layout_pin(text="vdd",
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layer="m2",
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self.left_vdd_pin = self.add_layout_pin(text="vdd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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# RIGHT vertical rails
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offset = vector(ur.x, ll.y) + vector(0, -2 * self.supply_rail_pitch)
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right_gnd_pin = self.add_layout_pin(text="gnd",
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layer="m2",
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# RIGHT vertical railsteac a 460
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offset = vector(ur.x, ll.y) + vector(2 * self.supply_rail_pitch - self.supply_rail_width,
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-2 * self.supply_rail_pitch)
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self.right_gnd_pin = self.add_layout_pin(text="gnd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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height=height + 2* supply_rail_spacing)
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offset = vector(ur.x, ll.y) + vector(self.supply_rail_pitch,
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offset = vector(ur.x, ll.y) + vector(1 * self.supply_rail_pitch - self.supply_rail_width,
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-1 * self.supply_rail_pitch)
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right_vdd_pin = self.add_layout_pin(text="vdd",
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layer="m2",
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self.right_vdd_pin = self.add_layout_pin(text="vdd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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@ -2260,47 +2267,47 @@ class layout():
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# BOTTOM horizontal rails
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offset = ll + vector(-2 * self.supply_rail_pitch,
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-2 * self.supply_rail_pitch)
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bottom_gnd_pin = self.add_layout_pin(text="gnd",
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layer="m1",
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self.bottom_gnd_pin = self.add_layout_pin(text="gnd",
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layer=h_layer,
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offset=offset,
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width=width,
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width=width + 2 * supply_rail_spacing,
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height=self.supply_rail_width)
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offset = ll + vector(-1 * self.supply_rail_pitch,
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-1 * self.supply_rail_pitch)
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bottom_vdd_pin = self.add_layout_pin(text="vdd",
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layer="m1",
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self.bottom_vdd_pin = self.add_layout_pin(text="vdd",
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layer=h_layer,
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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# TOP horizontal rails
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offset = vector(ll.x, ur.y) + vector(-2 * self.supply_rail_pitch,
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0)
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top_gnd_pin = self.add_layout_pin(text="gnd",
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layer="m1",
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2 * self.supply_rail_pitch - self.supply_rail_width)
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self.top_gnd_pin = self.add_layout_pin(text="gnd",
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layer=h_layer,
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offset=offset,
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width=width,
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width=width + 2 * supply_rail_spacing,
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height=self.supply_rail_width)
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offset = vector(ll.x, ur.y) + vector(-1 * self.supply_rail_pitch,
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self.supply_rail_pitch)
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top_vdd_pin = self.add_layout_pin(text="vdd",
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layer="m1",
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offset = vector(ll.x, ur.y) + vector(-1 * self.supply_rail_pitch,
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1 * self.supply_rail_pitch - self.supply_rail_width)
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self.top_vdd_pin = self.add_layout_pin(text="vdd",
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layer=h_layer,
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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# Remember these for connecting things in the design
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self.left_gnd_x_center = left_gnd_pin.cx()
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self.left_vdd_x_center = left_vdd_pin.cx()
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self.right_gnd_x_center = right_gnd_pin.cx()
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self.right_vdd_x_center = right_vdd_pin.cx()
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self.left_gnd_x_center = self.left_gnd_pin.cx()
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self.left_vdd_x_center = self.left_vdd_pin.cx()
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self.right_gnd_x_center = self.right_gnd_pin.cx()
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self.right_vdd_x_center = self.right_vdd_pin.cx()
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self.bottom_gnd_y_center = bottom_gnd_pin.cy()
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self.bottom_vdd_y_center = bottom_vdd_pin.cy()
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self.top_gnd_y_center = top_gnd_pin.cy()
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self.top_vdd_y_center = top_vdd_pin.cy()
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self.bottom_gnd_y_center = self.bottom_gnd_pin.cy()
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self.bottom_vdd_y_center = self.bottom_vdd_pin.cy()
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self.top_gnd_y_center = self.top_gnd_pin.cy()
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self.top_vdd_y_center = self.top_vdd_pin.cy()
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# Find the number of vias for this pitch
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self.supply_vias = 1
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@ -203,28 +203,29 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.replica_bitcell_array_inst.place(offset=0)
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self.add_end_caps()
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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ll = vector(-1 * self.dummy_col_insts[0].width, -1 * self.dummy_row_insts[0].height)
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self.translate_all(ll)
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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self.capped_rba_width = self.dummy_col_insts[0].width + self.dummy_row_insts[0].width + self.dummy_col_insts[1].width
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self.capped_rba_height = self.dummy_col_insts[0].height
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self.route_power_ring(self.supply_stack[2], self.supply_stack[0])
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self.route_supplies()
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self.route_unused_wordlines()
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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self.translate_all(ll)
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self.reset_coordinates()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def route_power_ring(self, v_layer, h_layer):
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self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height))
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self.supply_rail_width = drc["minwidth_m1"]
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self.supply_rail_pitch = 3 * self.supply_rail_width
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self.add_power_ring(v_layer, h_layer)
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def get_main_array_top(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_top()
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@ -288,13 +289,13 @@ class capped_replica_bitcell_array(bitcell_base_array):
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if "wl" in pin_name:
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# wordlines
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pin_offset = pin.ll().scale(0, 1)
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pin_width = self.width
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pin_width = self.capped_rba_width
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pin_height = pin.height()
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else:
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# bitlines
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pin_offset = pin.ll().scale(1, 0)
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pin_width = pin.width()
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pin_height = self.height
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pin_height = self.capped_rba_height
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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@ -309,55 +310,79 @@ class capped_replica_bitcell_array(bitcell_base_array):
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else:
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bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
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vdd_dir = bitcell.vdd_dir
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gnd_dir = bitcell.gnd_dir
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#vdd_dir = bitcell.vdd_dir
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#gnd_dir = bitcell.gnd_dir
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# vdd/gnd are only connected in the perimeter cells
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supply_insts = self.dummy_col_insts + self.dummy_row_insts
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#supply_insts = self.dummy_col_insts + self.dummy_row_insts
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inst = self.dummy_row_insts[1]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.top_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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# For the wordlines
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top_bot_mult = 1
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left_right_mult = 1
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.top_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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inst = self.dummy_row_insts[0]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.bottom_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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# There are always vertical pins for the WLs on the left/right if we have unused wordlines
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self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
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self.right_gnd_locs = self.route_side_pin("gnd", "right", left_right_mult)
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# This needs to be big enough so that they aren't in the same supply routing grid
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left_right_mult = 4
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.bottom_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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inst = self.dummy_col_insts[0]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.left_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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if gnd_dir == "V":
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self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
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self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
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# This needs to be big enough so that they aren't in the same supply routing grid
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top_bot_mult = 4
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if vdd_dir == "V":
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self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)
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self.bot_vdd_locs = self.route_side_pin("vdd", "bot", top_bot_mult)
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elif vdd_dir == "H":
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self.left_vdd_locs = self.route_side_pin("vdd", "left", left_right_mult)
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self.right_vdd_locs = self.route_side_pin("vdd", "right", left_right_mult)
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else:
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debug.error("Invalid vdd direction {}".format(vdd_dir), -1)
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for inst in supply_insts:
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for pin in inst.get_pins("vdd"):
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if vdd_dir == "V":
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self.connect_side_pin(pin, "top", self.top_vdd_locs[0].y)
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self.connect_side_pin(pin, "bot", self.bot_vdd_locs[0].y)
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elif vdd_dir == "H":
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self.connect_side_pin(pin, "left", self.left_vdd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_vdd_locs[0].x)
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for inst in supply_insts:
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for pin in inst.get_pins("gnd"):
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if gnd_dir == "V":
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self.connect_side_pin(pin, "top", self.top_gnd_locs[0].y)
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self.connect_side_pin(pin, "bot", self.bot_gnd_locs[0].y)
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elif gnd_dir == "H":
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self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.left_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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inst = self.dummy_col_insts[1]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.right_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.right_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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def route_unused_wordlines(self):
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"""
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Connect the unused RBL and dummy wordlines to gnd
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