luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

all control logic tests pass now

Browse Source
This commit is contained in:
Sam Crow
2023-09-27 16:38:57 -07:00
parent 1b13d4369e
commit a5412902c6
1 changed files with 0 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/Makefile
-8
View File
@@ -70,10 +70,6 @@ BROKEN_STAMPS = \
freepdk45/10_rom_wordline_driver_array_test.ok \
freepdk45/14_rom_array_test.ok \
freepdk45/16_rom_control_logic_test.ok \
freepdk45/16_control_logic_delay_multiport_test.ok \
freepdk45/16_control_logic_delay_rw_test.ok \
freepdk45/16_control_logic_delay_r_test.ok \
freepdk45/16_control_logic_delay_w_test.ok \
freepdk45/19_rom_bank_test.ok \
scn4m_subm/06_rom_decoder_test.ok \
scn4m_subm/07_rom_column_mux_array_test.ok \
@@ -128,10 +124,6 @@ BROKEN_STAMPS = \
sky130/15_local_bitcell_array_leftrbl_1rw_test.ok \
sky130/15_local_bitcell_array_norbl_1rw_1r_test.ok \
sky130/15_local_bitcell_array_norbl_1rw_test.ok \
sky130/16_control_logic_delay_multiport_test.ok \
sky130/16_control_logic_delay_rw_test.ok \
sky130/16_control_logic_delay_r_test.ok \
sky130/16_control_logic_delay_w_test.ok \
sky130/18_port_address_512rows_test.ok \
sky130/18_port_data_spare_cols_test.ok \
sky130/19_single_bank_2mux_test.ok \