mirror of https://github.com/VLSIDA/OpenRAM.git
Cleanup the new router
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@ -138,7 +138,7 @@ class router_tech:
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min_width = self.route_track_width * drc("minwidth_{0}".format(layer_name), self.route_track_width * min_wire_width, math.inf)
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return min_width
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def get_layer_space(self, zindex, width):
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def get_layer_space(self, zindex, width=None):
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""" Return the minimum spacing of a layer given wire width. """
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if width is None:
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width = self.get_layer_width(zindex)
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@ -18,7 +18,7 @@ class signal_escape_router(router):
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def __init__(self, layers, design, bbox=None):
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# `router_tech` contains tech constants for the router
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# `router` is the base router class
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router.__init__(self, layers, design, bbox)
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# New pins are the side supply pins
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@ -146,7 +146,7 @@ class signal_escape_router(router):
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def get_route_pairs(self, pin_names):
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""" """
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""" Return the pairs to be routed. """
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to_route = []
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for name in pin_names:
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@ -157,7 +157,7 @@ class signal_escape_router(router):
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def replace_layout_pins(self):
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""" """
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""" Replace the old layout pins with new ones around the perimeter. """
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for name, pin in self.new_pins.items():
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pin = graph_shape(pin.name, pin.boundary, pin.lpp)
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@ -18,7 +18,7 @@ class supply_router(router):
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def __init__(self, layers, design, bbox=None, pin_type=None):
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# `router_tech` contains tech constants for the router
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# `router` is the base router class
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router.__init__(self, layers, design, bbox)
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# Side supply pin type
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