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increase power ring crba width for drc

This commit is contained in:
Jesse Cirimelli-Low 2023-09-01 02:02:41 -07:00
parent c9a848550c
commit 066d00f44b
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/capped_replica_bitcell_array.py
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@ -223,7 +223,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
def route_power_ring(self, v_layer, h_layer):
self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height))
self.supply_rail_width = drc["minwidth_m1"]
self.supply_rail_width = drc["minwidth_m3"]
self.supply_rail_pitch = 6 * self.supply_rail_width
self.add_power_ring(v_layer=v_layer, h_layer=h_layer)