mirror of https://github.com/VLSIDA/OpenRAM.git
rom array compatability changes
This commit is contained in:
Sage Walker
SWalker
parent
1255a81487
commit
b0a0226e87
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@ -202,8 +202,8 @@ class rom_base_array(bitcell_base_array):
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pitch = drc["{0}_to_{0}".format(self.wordline_layer)]
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drain_l = self.cell_list[self.row_size][0].get_pin("D")
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drain_r = self.cell_list[self.row_size][self.column_size - 1].get_pin("D")
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gnd_l = drain_l.center() + vector(-0.5 * self.route_width, pitch + via_width + self.route_pitch)
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gnd_r = drain_r.center() + vector(0.5 * self.route_width, pitch + via_width + self.route_pitch)
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gnd_l = drain_l.center() + vector(-0.5 * self.route_width, 0.5 * pitch + via_width + self.route_pitch)
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gnd_r = drain_r.center() + vector(0.5 * self.route_width, 0.5 * pitch + via_width + self.route_pitch)
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self.add_layout_pin_rect_ends(name="gnd", layer=self.bitline_layer, start=gnd_l, end=gnd_r)
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@ -310,7 +310,7 @@ class rom_base_array(bitcell_base_array):
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directions="nonpref")
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self.add_via_stack_center(offset=tap_pos,
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from_layer=self.active_stack[2],
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to_layer=self.wordline_layer)
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to_layer=self.wordline_layer, directions="nonpref")
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self.gnd_taps.append(self.add_layout_pin_rect_center("gnd_tap", self.wordline_layer, tap_pos))
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def place_precharge(self):
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@ -326,6 +326,10 @@ class rom_base_array(bitcell_base_array):
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def place_bitline_contacts(self):
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if "li" in layer:
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output_layer = "m1"
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else:
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output_layer = "m3"
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rail_y = self.precharge_inst.get_pins("vdd")[0].cy()
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for bl in range(self.column_size):
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@ -340,9 +344,12 @@ class rom_base_array(bitcell_base_array):
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output_pos = vector(corrected.x, rail_y)
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self.add_segment_center(self.bitline_layer, corrected, output_pos)
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if output_layer != self.bitline_layer:
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self.add_via_stack_center(from_layer=self.bitline_layer, to_layer=output_layer, offset=corrected)
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self.add_layout_pin_rect_center(self.bitline_names[0][bl], self.bitline_layer, output_pos )
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self.add_segment_center(output_layer, corrected, output_pos)
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self.add_layout_pin_rect_center(self.bitline_names[0][bl], output_layer, output_pos )
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def route_precharge(self):
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for bl in range(self.column_size):
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@ -15,10 +15,16 @@ from openram.tech import drc
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class rom_base_cell(design):
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def __init__(self, name="", bitline_layer="li", bit_value=1, add_well=False):
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def __init__(self, name="", bitline_layer=None, bit_value=1, add_well=False):
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super().__init__(name)
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self.bit_value = bit_value
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self.bitline_layer = bitline_layer
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if bitline_layer is None and OPTS.tech_name == "sky130":
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self.bitline_layer = "li"
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elif bitline_layer is None:
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self.bitline_layer = "m1"
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else:
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self.bitline_layer = bitline_layer
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self.add_well=add_well
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self.create_netlist()
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self.create_layout()
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@ -41,6 +47,7 @@ class rom_base_cell(design):
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# Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules
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def setup_drc_offsets(self):
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self.bitline_width = drc(f"minwidth_{self.bitline_layer}")
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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def add_boundary(self):
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@ -50,9 +57,7 @@ class rom_base_cell(design):
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#cell width with offsets applied, height becomes width when the cells are rotated
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width = self.cell_inst.height + 2 * self.poly_extend_active
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# make the cells square so the pitch of wordlines will match bitlines
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if width > height:
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self.width = width
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self.height = width
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@ -62,7 +67,6 @@ class rom_base_cell(design):
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super().add_boundary()
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def add_modules(self):
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self.nmos = factory.create(module_type="ptx",
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@ -72,7 +76,6 @@ class rom_base_cell(design):
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add_drain_contact=self.bitline_layer
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)
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def create_tx(self):
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self.cell_inst = self.add_inst( name=self.name + "_nmos",
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mod=self.nmos,
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@ -82,7 +85,6 @@ class rom_base_cell(design):
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else:
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self.connect_inst(["bl_h", "wl", "bl_l", "gnd"])
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def add_pins(self):
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if self.bit_value == 0 :
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pin_list = ["bl", "wl", "gnd"]
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@ -95,10 +97,7 @@ class rom_base_cell(design):
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def place_tx(self):
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# sizing_offset = self.cell_inst.height - drc["minwidth_tx"]
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tx_offset = vector(self.poly_extend_active + self.cell_inst.height + self.poly_size,- 0.5 * self.contact_width - self.active_enclose_contact)
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# add rect of poly to account for offset from drc spacing
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# self.add_rect_center("poly", poly_offset, self.poly_extend_active_spacing, self.poly_width)
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self.cell_inst.place(tx_offset, rotate=90)
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@ -113,13 +112,10 @@ class rom_base_cell(design):
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end = poly_offset + vector(self.poly_size, 0)
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self.add_segment_center("poly", start, end)
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def place_bitline(self):
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start = self.get_pin("D").center()
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end = start + vector(0, 2 * self.active_enclose_contact + 0.5 * self.contact_width + self.active_space)
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self.add_segment_center(self.bitline_layer, start, end)
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end = start + vector(0, 2 * self.active_enclose_contact + self.contact_width + self.active_space)
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self.add_segment_center(self.bitline_layer, start, end, self.bitline_width * 2)
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def short_gate(self):
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self.add_segment_center(self.bitline_layer, self.get_pin("D").center(), self.get_pin("S").center())
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@ -13,9 +13,9 @@ from openram.tech import drc
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class rom_poly_tap(design):
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def __init__(self, name="", cell_name=None, tx_type="nmos", strap_layer="m2", add_active_tap=False, place_poly=None):
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def __init__(self, name="", cell_name=None, tx_type="nmos", strap_layer="m2", add_active_tap=False, place_poly=False):
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super().__init__(name, cell_name)
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self.strap_layer=strap_layer
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self.strap_layer = strap_layer
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self.tx_type = tx_type
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self.add_tap = add_active_tap
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if place_poly is None:
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@ -36,9 +36,10 @@ class rom_poly_tap(design):
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self.place_via()
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self.add_boundary()
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self.extend_poly()
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if self.add_tap or self.place_poly:
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self.place_active_tap()
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self.extend_poly()
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def add_boundary(self):
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contact_width = self.poly_contact.width
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@ -59,9 +60,14 @@ class rom_poly_tap(design):
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contact_x = contact_width * 0.5 + self.contact_x_offset
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self.contact_offset = vector(contact_x, contact_y)
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if OPTS.tech_name == "sky130":
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directions="pref"
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else:
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directions="nonpref"
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self.via = self.add_via_stack_center(from_layer="poly",
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to_layer=self.strap_layer,
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offset=self.contact_offset)
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offset=self.contact_offset,
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directions=directions)
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self.add_layout_pin_rect_center("poly_tap", self.strap_layer, self.contact_offset)
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def extend_poly(self):
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@ -69,8 +75,8 @@ class rom_poly_tap(design):
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if self.tx_type == "pmos":
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y_offset = -self.height
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start = self.via.center() + vector(0, y_offset)
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self.add_segment_center("poly", start, vector(self.via.cx() + self.pitch_offset, self.via.cy() + y_offset))
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if self.place_poly:
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self.add_segment_center("poly", start, vector(self.via.cx() + self.pitch_offset, self.via.cy() + y_offset))
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self.add_segment_center("poly", start, vector(0, self.via.cy() + y_offset))
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def place_active_tap(self):
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@ -125,7 +125,6 @@ class rom_precharge_array(design):
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# columns are bit lines
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cell_x = 0
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for col in range(self.cols):
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if col % self.strap_spacing == 0:
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@ -136,7 +135,6 @@ class rom_precharge_array(design):
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cell_x += self.poly_tap.pitch_offset
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self.pmos_insts[col].place(vector(cell_x, cell_y))
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self.add_label("debug", "li", vector(cell_x, cell_y))
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cell_x += self.pmos.width
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self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height))
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@ -150,7 +148,6 @@ class rom_precharge_array(design):
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self.add_layout_pin_rect_center(bl, self.bitline_layer, source_pin.center())
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def route_supply(self):
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self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer)
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def connect_taps(self):
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@ -26,7 +26,10 @@ class rom_precharge_cell(rom_base_cell):
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self.extend_well()
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def add_modules(self):
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width = pgate.nearest_bin("pmos", drc["minwidth_tx"])
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if OPTS.tech_name == "sky130":
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width = pgate.nearest_bin("pmos", drc["minwidth_tx"])
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else:
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width = drc("minwidth_tx")
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self.pmos = factory.create(module_type="ptx",
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module_name="pre_pmos_mod",
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tx_type="pmos",
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@ -60,8 +63,7 @@ class rom_precharge_cell(rom_base_cell):
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def place_tap(self):
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source = self.cell_inst.get_pin("S")
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tap_y = source.cy() - self.contact_width - 2 * self.active_enclose_contact - self.active_space
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tap_y = source.cy() - self.contact_width - 5 * self.active_enclose_contact - self.active_space
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self.tap_offset = abs(tap_y)
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pos = vector(source.cx(), tap_y )
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@ -83,4 +85,8 @@ class rom_precharge_cell(rom_base_cell):
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self.remove_layout_pin("S")
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def place_bitline(self):
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pass
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def short_gate(self):
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print("not shorting")
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pass
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