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Author SHA1 Message Date
Matthias Koefferlein b8c82c4f8b Updated copyright notice to 2020 2020-01-05 00:59:43 +01:00
Matthias Koefferlein 811560094a Updated tests. 2020-01-04 21:19:06 +01:00
Matthias Koefferlein 833edf53b2 Implemented #462 (Generalize MOS transistor extraction to other gate figures) 2020-01-02 22:20:45 +01:00
Matthias Koefferlein c4636cebdb Fixed #458 (Array instance net tracing bug) 2019-12-23 20:38:17 +01:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein da1ac3661f WIP: bugfix of refactoriung, update test data. 2019-12-15 00:16:47 +01:00
Matthias Koefferlein 4acc4b96e2 First attempt to fix the issue 
Problem was caching which did not take into account the array nature
of instances.

This fix also moves the cache one level below so it is effective also
when instance tree traversal happens. This might speed up things too.

Needs testing.
 2019-12-09 21:37:07 +01:00
Matthias Koefferlein 3b9beb0d49 Fixed #438 (error on redefinition of subcircuit in SPICE) 2019-12-07 23:39:39 +01:00
Matthias Koefferlein 0f1dc1d191 Refine pin mismatch handling so that only 'not used' nets will make a pin match against null. 2019-11-24 16:40:45 +01:00
Matthias Koefferlein aa28aa807a Unit tests fixed and a bugfix in the netlist compare 
One unit test was failing because the netlist compare did not
properly consider dropped pins:
* A severe bug ("g1" should be "g2")
* Incomplete detection of dropped pins upwards in the hierarchy

The general pin and net mapping scheme has been enhanced so that
net mapping to "0" is valid (this will happen in case of dropped
pins) and this condition is used to detect pins without match
requirement.
 2019-11-23 22:04:25 +01:00
Matthias Koefferlein 1309aa59cb Merge branch 'master' into issue-425 2019-11-23 01:55:28 +01:00
Matthias Koefferlein 7de90ae595 Merge branch 'issue-417' 2019-11-23 01:46:38 +01:00
Matthias Koefferlein 79f4f8bc57 Update unit test for issue-417 branch. 2019-11-23 01:45:56 +01:00
Matthias Koefferlein d5506a176a WIP: first implementation - needs testing. 2019-11-23 01:20:22 +01:00
Matthias Koefferlein 2757b22da6 Resolved conflicts for issue-419 merge 2019-11-22 23:34:03 +01:00
Matthias Köfferlein a792cf4c1e
Merge pull request #424 from KLayout/issue-407 
Issue 407
 2019-11-22 23:12:44 +01:00
Matthias Köfferlein ac7e17ffcb
Merge pull request #422 from KLayout/issue-406 
Issue 406
 2019-11-22 23:12:16 +01:00
Matthias Köfferlein c8cf8122b6
Merge pull request #414 from KLayout/issue-411 
Issue 411
 2019-11-22 23:11:24 +01:00
Matthias Koefferlein 247bfa9ac5 Implemented #407 (variables in technology base path) 
The implementation uses extrapolation of strings in the
"Expressions" framework.

There is how:
* $(tech_name) -> substituted by the technology name
* $(tech_dir) -> substituted by the directory the technology file is stored in
* $(tech_file) -> substituted by the absolute path to the tech file
* $(appdata_path) -> substituted by KLayout's home directory (e.g. ~/.klayout)
* $(env('X')) -> substituted by the environment variable $X
 2019-11-21 21:37:00 +01:00
Matthias Koefferlein 6648b53822 Fixed issue #419 (multiple top circuits after flatten of netlist) 
The problem is solved by always producing subcircuits for cell
instances, even if there are no connections.

The netlist comparer had to be adjusted too because subcircuits
without pins were used for representing "unknown" subcircuit pairing.

In addition, this patch should lead to a better matching of
parallel subcircuit configurations where two different subcircuits
are entirely parallel.
 2019-11-20 21:56:12 +01:00
Matthias Koefferlein 6c7ceb74dc Enhanced intersections algorithm so that the generated points won't overlay with finite edges from the AND part 2019-11-19 21:19:36 +01:00
Matthias Koefferlein 9af662a512 WIP: try to avoid duplicate intersection points by eliminating those. Problem persists: intersection points may be duplicates of edges arising from AND 2019-11-18 23:14:24 +01:00
Matthias Koefferlein 990961e5f4 Fixed #411 (multiple device extractors for same class) 2019-11-17 23:12:50 +01:00
Matthias Koefferlein 8dddc4000f Also write the net properties to GDS or OASIS 
"build_nets" will now write the net's properties
to the generated net shapes.
This might enable interesting applications.
 2019-11-13 23:09:09 +01:00
Matthias Koefferlein bb3aed5773 Merge branch 'master' of https://github.com/KLayout/klayout into netlist_properties 2019-11-13 00:59:29 +01:00
Matthias Koefferlein 876487edde Added persistency of the netlist object properties into L2N/LVSDB files 2019-11-13 00:06:29 +01:00
Matthias Koefferlein d060147713 Enhancements for the netlist object properties 
- more memory efficient (single pointer only)
- iterator for properties
- NetlistObject#property_keys in GSI
 2019-11-12 23:00:49 +01:00
Matthias Koefferlein 86e041cd51 Updated test data. 2019-11-11 23:03:40 +01:00
Matthias Koefferlein 0ce06125ca Introducing netlist object properties. 2019-11-11 07:02:02 +01:00
Matthias Koefferlein 4a212e8db6 Added tests for Region#scale_and_snap and Region#snap 2019-11-07 23:33:54 +01:00
Matthias Koefferlein 988b1e563f Added unit test for DeepRegion::snap 2019-11-07 23:11:34 +01:00
Matthias Koefferlein 318efbf7b0 Fixed 'scale_and_snap' feature 2019-11-07 22:54:16 +01:00
Matthias Koefferlein 4924d0269c Fixed #400, added tests. 2019-11-06 23:28:16 +01:00
Matthias Koefferlein 3cc38fcfc2 Solved ambiguous bus resolution problem. 2019-10-29 23:26:17 +01:00
Matthias Koefferlein 15fa99c128 WIP: bugfix ambiguous bus-like pins and net compare. 2019-10-29 22:53:37 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein 373a3db1ec WIP: netlist comparer - increase default depth and added test 
The test is specific for symmetric circuits with manifold
symmetry axes.
 2019-10-24 23:58:30 +02:00
Matthias Koefferlein ac479c30bc Fixed unit tests. 2019-10-24 00:23:03 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein 611f62e73f Removed debug leftover code 2019-10-17 22:47:43 +02:00
Matthias Koefferlein 2325e1bce4 Merge branch 'dvb' into pull_feature 2019-10-04 22:58:52 +02:00
Matthias Koefferlein ef56264f64 Fixed a regular arrays issue with begin_touching 
In case of 1d arrays with a or b == (0,0), the iterator
was always delivering all items, not just the touching ones.
 2019-10-04 22:45:23 +02:00
Matthias Koefferlein 5ed41cc345 Merge branch 'master' into pull_feature 2019-10-03 14:32:25 +02:00
Matthias Koefferlein e1d77a1476 pull_interacting for edges/edges and edges/regions, some enhancements and bug fixes 
Bug fixes:
- use dist 1 to cover touching case properly in local processor
- handling of raw mode and is_merged state

Additional tests
 2019-10-03 13:08:37 +02:00
Matthias Koefferlein 76b8bd3279 Fixed several issues with raw mode/merged semantics and many Region and Edges methods. Added edge/edge pull and edge/polygon pull. 2019-10-03 01:46:49 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 506cfc1c6f WIP: attempt to retain nets which don't have active elements but pins. This is supposed to simplify debugging in case of fake pins. When removing those nets, the pin is very difficult to find. 2019-09-30 20:58:55 +02:00
Matthias Koefferlein d69c60a5c5 Enabled net tracing for heavily decomposed polygons 2019-09-19 00:13:14 +02:00
Matthias Koefferlein 56084b6b59 Merge branch 'dvb' 2019-09-08 20:07:16 +02:00
Matthias Koefferlein e2cc0c48b1 Provide flat and hierarchical 'trace all nets' feature, added Netlist#flatten. 2019-09-06 23:13:21 +02:00
Matthias Koefferlein fa72885020 issue #317: provide undo combination for the paste+move sequence in 'interactive paste'. Same for 'interactive dup' 2019-09-04 23:47:05 +02:00
Matthias Koefferlein 5cfadad54f Updated test data. 2019-08-30 11:01:00 +02:00
Matthias Koefferlein 2a8f4c9610 Updated test data. 2019-08-30 10:52:51 +02:00
Matthias Koefferlein 550e2622bf Put more amphasis on net names to resolve ambiguities 
The problem was that with the floating test case, the
ambiguity resolution sometimes assigned the wrong pins
and floating pins/connected pins were swapped.

One option is to make the ambiguity resolver consider
the pin connection state when tenatively evaluating
nodes.

Another option is to put more emphasis on net names
and use them for ambiguity resolution. This has helped
here.
 2019-08-30 10:24:55 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein b1acfe9587 Tried a better deal with floating pins 
1.) is_floating is now only true if there is no device
    and no subcircuit on a net. This means we only purge
    nets if they are really floating. So far we purged
    nets without pins which lead to the mismatch:

    Before purge:
      Layout:            (net) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    After purge:
      Layout:           (null) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    (null does not match any net)

2.) circuit pin matching was a bit picky. Only when
    one circuit did not have pins, matching was sloppy.

    In real cases however, circuits may have unconnected
    pins:
    - top level pins without a counterpart (no label)
    - subcircuits pins which are not used

    We catch both cases by refining the match: if a pin
    is not used, it does not need to match against
    any other pin. It's reported as "matching against null"
    though.
 2019-08-29 22:25:59 +02:00
Matthias Koefferlein b0aa9b6540 Spice reader test compatible with Windows (three-digit exponential) 2019-08-21 23:03:24 +02:00
Matthias Koefferlein 45cdefcf9a Provide strict mode for device classes, dmos3/dmos4 for LVS 2019-08-20 23:12:17 +02:00
Matthias Koefferlein b7c83eaaa6 Spice reader: subcircuits w/o pins 
This happens for subcircuits which only
connect to global nets.

Plus: ".global" now accepts more than just one net
 2019-08-19 23:00:24 +02:00
Matthias Koefferlein 1bc03c3b79 Implement "M" parameter for Spice 
This implementation is pretty simplistic and
applies "M" the following way:
* R: R(final) = R/M
* L: L(final) = L/M
* C: C(final) = C*M
* M: W(final) = W*M
* D: A(final) = A*M
* Q: AE(final) = AE*M

The other parameters (specifically the other
geometry parameters) are not scaled yet.
 2019-08-19 22:51:22 +02:00
Matthias Koefferlein 24b985f32e Better .include for Spice reader 
* .inc is allowed as synonym
* Paths can be URL's (with HTTP)
* Relative resolution of paths/URL's vs. parent of .include
 2019-08-19 21:45:40 +02:00
Matthias Köfferlein 15f45fb09d
Merge pull request #327 from KLayout/query-performance-fix 
Fix for layout query performance improvement: needs to check for qual…
 2019-08-19 19:37:15 +02:00
Matthias Koefferlein fe4396d872 Merge branch 'issue-306' 2019-08-19 00:03:39 +02:00
Matthias Koefferlein e9eed3842b Fix for layout query performance improvement: needs to check for qualified cell name (with lib), not pure cellname 2019-08-18 19:09:07 +02:00
Matthias Koefferlein 8981ed434a First fix for issue-306: some polygons are not recognized as rounded, more robust radius extraction. 2019-08-17 23:55:49 +02:00
Matthias Koefferlein dfd713016b Added some unit tests for performance improvement of queries. 2019-07-29 22:36:39 +02:00
Matthias Koefferlein 0dcfeabaf4 Query performance improvement for the cell tree recursion case by introducing optimization hints ('filter state objectives') 2019-07-29 22:27:36 +02:00
Matthias Koefferlein 169cc5246d WIP: updated golden data for new device sorting in cross reference. 2019-07-27 20:37:41 +02:00
Matthias Koefferlein b4fa4b1bae Flattening of layout with circuit flattening. 
Technically, the layout isn't flattened, but connections are made
which allow regenerating the layout even after the circuit
has been flattened.
 2019-07-27 00:37:22 +02:00
Matthias Koefferlein afb5cea576 Added "device_scaling" to LVS 
Plus: added some missing files

Implementation details:
* scaling factor was introduced in DeviceExtractor::extract
* for easy implementation this is available in "sdbu"
* "sdbu" is made available in GSI
* to test this, the db::compare_netlist had to be enhanced to
  exactly check device parameters
* enhancement of LVS script framework and doc updates
 2019-07-24 00:16:47 +02:00
Matthias Koefferlein 14d9689498 Added .global to Spice reader. 2019-07-22 23:02:31 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00
Matthias Köfferlein b3e9915259 Provide special LVS test golden data for Windows (slight differences in shape order etc.) 2019-07-16 00:40:43 +02:00
Matthias Köfferlein 9820e57031 Don't write third terminal for R or C (WithBulk variants) 2019-07-15 23:19:03 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein 7bc4acd8f6 WIP: new version of subcircuit match algorithm - needs refactoring. 2019-07-11 23:14:53 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein 71777670de Fixed unit tests. 2019-07-04 01:24:19 +02:00
Matthias Koefferlein ef1441e546 WIP: fixed unit tests. 2019-06-28 17:08:04 +02:00
Matthias Koefferlein 37012efba0 WIP: fixed unit tests, bug fix in DeepRegion -> and and not shall return a DeepRegion always. 2019-06-24 20:56:20 +02:00
Matthias Koefferlein 624811d55e WIP: fixed a basic issue with empty layers 
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
 2019-06-23 23:44:15 +02:00
Matthias Koefferlein 621c3f74ed WIP: reader delegate - GSI binding, tests. 2019-06-22 22:03:32 +02:00
Matthias Koefferlein 343e340e22 WIP: SPICE reader delegate, unit tests + debugging 2019-06-22 19:44:33 +02:00
Matthias Koefferlein d174fb73fd WIP: preparations for SPICE reader delegate. 2019-06-22 18:37:32 +02:00
Matthias Koefferlein 9647c94c68 WIP: added NE parameter for BJT3/4, AE and NE are primary parameters now. 2019-06-21 23:41:08 +02:00
Matthias Koefferlein a4d2be7fbf Merge remote-tracking branch 'origin/master' into dvb 2019-06-19 23:14:27 +02:00
Matthias Köfferlein 2ef403e0ac
Merge pull request #282 from KLayout/issue-281 
Fixed #281 (proper reporting of width/space violations in the kissing…
 2019-06-18 18:44:41 +02:00
Matthias Koefferlein 303cda6981 Fixed #277 (min_coherence not recognized by region size) 2019-06-17 21:40:37 +02:00
Matthias Koefferlein 2389d2b391 Fixed #281 (proper reporting of width/space violations in the kissing-corner case) 2019-06-17 20:48:07 +02:00
Matthias Koefferlein a91c3d3a4e WIP: fixed BJT4 class, added RBA tests for new device classes. 2019-06-15 21:11:15 +02:00
Matthias Koefferlein e939d51104 WIP: BJT4 device, more parameters for resistor (W,L), BJT devices for Spice writer, tests updated 2019-06-15 18:22:04 +02:00
Matthias Koefferlein 1b2a611d83 WIP: diode extraction test. 2019-06-15 09:34:04 +02:00
Matthias Koefferlein 0b5db06ca8 WIP: tests for BJT extraction 2019-06-14 23:45:04 +02:00
Matthias Koefferlein 4212a783a5 WIP: test cases for device extractors R/C with bulk 2019-06-14 21:21:11 +02:00
Matthias Koefferlein 020b874083 WIP: more device classes - unit tests for classes 2019-06-14 20:41:38 +02:00
Matthias Koefferlein 0d623bc57a Avoid netlist extraction issues with duplicate instances 
So far, duplicate instances have lead to net propagation
into parent cells and floating nets. This is fixed by ignoring
duplicate instances where possible.
 2019-06-13 13:33:28 +02:00
Matthias Koefferlein ebd00c186b Enhancements for net export feature 
- some refactoring
- better performance (was slow because layer iteration
  was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
  produced. For this a new argument is added to
  LayoutToNetlist::create_cell_mapping (nets) which
  allows selecting the nets for which a cell mapping
  is requested
 2019-06-12 22:55:24 +02:00
Matthias Koefferlein 7c220c63e1 Functional netlist hierarchy tree. 2019-06-06 01:36:07 +02:00
Matthias Koefferlein 7d6237a90a Unescaping of net names on Spice reader -> writer/reader should be self-compatible. 2019-05-31 22:55:09 +02:00
Matthias Koefferlein 985cffc099 Unique net names for Spice netlist writer 2019-05-31 22:19:51 +02:00
Matthias Koefferlein c684633dd6 Some enhancements for netlist extraction and writer 
* Spice writer can now be configure to skip the debug
  comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
 2019-05-31 00:11:28 +02:00
Matthias Koefferlein d4634f8620 Try to establish reproducability of clock tree compare test. 2019-05-30 07:12:49 +02:00
Matthias Koefferlein 1935ee7ff9 Tried to fix unit tests for MSVC 2019-05-29 22:09:39 +02:00
Matthias Koefferlein dea2b76dc8 Added unit tests for res and cap device extractors. 2019-05-29 21:35:02 +02:00
Matthias Koefferlein 10667d8e35 Bugfixed last commit, fixed unit tests. 2019-05-29 00:51:42 +02:00
Matthias Koefferlein 2bf3f3d5c9 Fixed unit tests, bug fixes in netlist DB model. 2019-05-26 18:28:35 +02:00
Matthias Koefferlein 252622e3f8 Fixed unit tests, support floating pins for netlist compare 2019-05-20 23:48:07 +02:00
Matthias Koefferlein 625b173379 Reworked l2n and lvsdb format such that reading/writing gets more reproducible: maintain unnamed state of devices, subcircuits and pins 2019-05-20 22:33:23 +02:00
Matthias Koefferlein 834dcc7474 WIP: LVSDB reader/writer fixes 2019-05-19 23:42:31 +02:00
Matthias Koefferlein ea8320dcf8 WIP: LVSDB reader/writer: bugfixes, refactoring, tests. 2019-05-19 22:55:03 +02:00
Matthias Koefferlein 81e512e1cd WIP: Debugging of LVS DB writer 2019-05-19 10:13:20 +02:00
Matthias Koefferlein 65ea72c569 WIP: netlist cross reference - refactoring of sorting, more robust 2019-05-16 23:26:49 +02:00
Matthias Koefferlein 95caca1dd5 WIP: netlist cross reference - tests and bugfixes 2019-05-16 22:43:28 +02:00
Matthias Koefferlein 924daa65b7 WIP: tests for netlist cross ref. 2019-05-16 00:09:06 +02:00
Matthias Koefferlein 6f689863b6 Fixed MSVC build, fixed unit tests. 2019-05-10 21:09:19 +02:00
Matthias Koefferlein ea28530c55 L2N: combined device persistance (complex concept - needs simplification?) 2019-05-10 00:15:51 +02:00
Matthias Koefferlein c33fd40ec9 Switched l2n format to relative mode by default (relative mode is an option and maybe shorter) 2019-05-04 23:06:18 +02:00
Matthias Koefferlein 548f16f1df WIP: tried to provide a more consistent net building feature (here: building hierarchical nets with properties as net annotation - needs cell variants if properties are assigned to subcells too) 2019-05-04 00:37:38 +02:00
Matthias Koefferlein 2aaec56adb WIP: netlist browser - extended the net export scheme of build_net to support net annotation and flattening. 2019-05-03 23:33:37 +02:00
Matthias Koefferlein 7f9da5e8de Introduced concept of device class templates 
This concept allows to persist at least the standard
(built-in) device classes into L2N DB files. This way
device classes are persisted.
 2019-04-23 19:44:07 +02:00
Matthias Koefferlein 8121f70e65 Netlist compare: Net mismatches reported if nets don't match but we still will proceed 2019-04-18 00:01:21 +02:00
Matthias Koefferlein 197d99ab62 Unit test fixed. 2019-04-16 07:10:34 +02:00
Matthias Koefferlein eabf558186 netlist exaction: selective net joining with labels 
Now, a glob pattern can be used to identify the labels
which implicitly join nets. Also, net joining now
only happens on top level.
 2019-04-15 23:24:27 +02:00
Matthias Koefferlein 9f3bea92fb WIP: less strict pin matching (for top levels with/without pins). Fixed tests. 2019-04-14 19:22:07 +02:00
Matthias Koefferlein 699e94a45f WIP: added configuration options (complexity, depth) for net compare 2019-04-14 19:11:42 +02:00
Matthias Koefferlein 92524dcf57 WIP: netlist compare - bugfixed latest version and updated tests. 2019-04-13 19:56:08 +02:00
Matthias Koefferlein 4e85ae7db0 WIP: netlist compare (better backtracking) 2019-04-13 02:48:10 +02:00
Matthias Koefferlein 187baf2941 WIP: enhanced backtracking of netlist compare. 2019-04-12 00:15:36 +02:00
Matthias Koefferlein f34d161e2f WIP: new backtracking algorithm for net matching. 2019-04-09 23:13:40 +02:00
Matthias Koefferlein 2e9422a753 Netlist compare: a little less freedom when picking derived net pairs ... 2019-04-08 21:32:41 +02:00
Matthias Koefferlein 7cdd40dabb Netlist compare: more detailed derivation of net assignments from known nets (pairing by deduction) 2019-04-08 21:21:34 +02:00
Matthias Koefferlein c474fa6550 Bugfix: Spice reader needs to transform length units to micrometer 2019-04-07 11:09:08 +02:00
Matthias Koefferlein f6836b96a2 WIP: some enhancements 
Spice writer: don't prefix model name with "M"
Added "device_class_mismatch" message to netlist compare
Assertion if device classes or circuits are nil on
"same_..."
 2019-04-07 10:15:57 +02:00
Matthias Koefferlein df2bd5e80a Netlist: flatten subcircuits, circuits 2019-04-06 23:36:08 +02:00
Matthias Koefferlein aad52b77ba Netlist compare: added the ability to filter small caps and high resistance devices 2019-04-06 19:46:13 +02:00
Matthias Koefferlein da5680ef24 Netlist compare: configurable device parameter compare scheme. 2019-04-06 15:19:43 +02:00
Matthias Koefferlein 52fb8b0f65 Merge remote-tracking branch 'remotes/origin/master' into dvb 2019-04-04 07:35:43 +02:00
Matthias Koefferlein 8e9f15669f WIP: utilizing netlist compare for DRC checks as well 
+ Some enhancements (e.g. enable pin swapping for pins
  without names and devices or subcircuits)
 2019-04-02 22:39:29 +02:00
Matthias Koefferlein 89ffd7e3da WIP: Simple SPICE reader. 2019-04-01 22:46:33 +02:00
Matthias Koefferlein 9613ad72c8 WIP: netlist compare - using it for more tests 
Issue solved: some circuit pins may not have a net - these
need to be ignored.

Requirement: all pins with a net must be mapped.

Detached pins are not present in the mapping table.
A dummy mapping table was introduced to allow dropping
of pins in the second circuit too.

Output of compare should not depend on memory location
anymore and pin mismatch reporting should include all
pins.
 2019-03-31 23:59:43 +02:00
Matthias Koefferlein 06e326dfd9 WIP: netlist compare - some more tests by netlist compare. Needs fixing. 2019-03-31 19:00:42 +02:00
Ruben Undheim 5d26cf4c77 Spelling errors in code and comments fixed 2019-03-31 15:25:18 +00:00
Matthias Koefferlein b391b4510f WIP: can compare empty circuits now 
Empty circuits play a role as abstracts. They
are compared by using the pin names the nets
are attached to. The implementation change is:
* nodes without device terminals or subcircuit pins
  are compared through their net properties (count
  and name of pins attached)
* some enhancements of the net string serializer
  have been made to account for pin name mismatches.
 2019-03-31 09:53:51 +02:00
Matthias Koefferlein 2452c72d2d WIP: netlist compare deployed for netlist extractors 
Some enhancements were required:
* Clusters left over from joined clusters must not be
  turned into nets: this leads to dummy nets.
* null Nets can happen as targets of edges. Don't assert
  in this case but treat null nets as identical for both
  netlists.
* Don't resolve ambiguous nets if there are options to
  do this non-ambiguously.
* logger can be null
* Added compare_netlists to dbTestSupport
 2019-03-30 23:04:57 +01:00
Matthias Koefferlein f06d435b05 WIP: netlist comparer - moved into it's own files. 2019-03-29 00:37:45 +01:00
Matthias Koefferlein e8d59504dd WIP: netlist compare - forced matching of circuits. 2019-03-29 00:13:13 +01:00
Matthias Koefferlein d255617051 WIP: netlist compare - tests for device class equivalence mapping, added Netlist#device_class_by_name 2019-03-28 18:01:22 +01:00
Matthias Koefferlein cefd6e91cf WIP: some refactoring, netlist compare. Goal: support explicit device class and circuit mapping. 2019-03-27 23:17:35 +01:00
Matthias Koefferlein b44a55d901 WIP: netlist compare - pin swapping. 2019-03-26 23:38:36 +01:00
Matthias Koefferlein 46cd80d606 WIP: netlist compare - terminal swapping of devices. 2019-03-26 22:05:08 +01:00
Matthias Koefferlein e0cb3f6303 WIP: netlist compare - subcircuit matching enhanced. 2019-03-26 20:54:49 +01:00
Matthias Koefferlein 93d2341bc7 WIP: netlist compare 2019-03-26 00:10:10 +01:00
Matthias Koefferlein fec2348d97 WIP: Net compare. 2019-03-25 23:26:46 +01:00
Matthias Koefferlein 1a30a3919d WIP: Net compare with subcircuits. 2019-03-25 22:14:16 +01:00
Matthias Koefferlein 55052038ea WIP: netlist compare 2019-03-24 21:14:08 +01:00
Matthias Koefferlein bb2d3765b8 WIP: netlist compare, ambiguous net resolution, device mapping. 2019-03-24 00:45:58 +01:00
Matthias Koefferlein 25b7ab9dab WIP: netlist comparer 2019-03-23 10:31:29 +01:00
Matthias Koefferlein 7042cdb98b Ported netlist normalization for #246 merge (unit test compatibility windows/linux) 2019-03-22 21:54:45 +01:00
Matthias Köfferlein d1acd722ad
Merge pull request #246 from KLayout/issue-245 
Issue 245
 2019-03-22 21:49:39 +01:00
Matthias Koefferlein 4e63b38092 Further normalization of Spice test files (unit tests) 2019-03-22 21:47:52 +01:00
Matthias Koefferlein 5dfc609724 Normalize netlists before compare for windows/linux compatibility. 2019-03-22 17:51:37 +01:00
Matthias Koefferlein 9356f32026 Fixed issue-245 (support Spice netlist with names instead of numbers) 
The option is in the Spice writer (writer.use_net_names=true).
 2019-03-21 23:34:16 +01:00
Matthias Koefferlein e424a88c90 WIP: netlist compare algo 
1.) Can identify transistor netlists without subcircuits
2.) Ambiguities stay unresolved

Next steps: assign ambiguous nets one by one and continue
in case of ambiguitites.
 2019-03-21 22:13:23 +01:00
Matthias Koefferlein c568838bbe WIP: netlist compare 2019-03-20 23:00:43 +01:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein d7eb9162ce WIP: unified to_string/to_parsable_string of db::Netlist, step 1 2019-03-18 19:28:20 +01:00
Matthias Koefferlein e4078ca750 String serialization for netlists. 2019-03-18 02:00:33 +01:00
Matthias Koefferlein 57fb764f16 Removed ambiguity for 64bit coordinate builds. 2019-03-12 00:09:52 +01:00
Matthias Koefferlein 510c675d21 Test cases for DRC-based net extraction and flat extraction 
Flat extraction requires that texts of subcells are not
considered. Otherwise they pollute the net namespace of
the top cell.
 2019-03-10 19:35:13 +01:00
Matthias Koefferlein 37cc84908e Updated test because of edge pair normlization 2019-03-09 20:25:45 +01:00
Matthias Koefferlein 6932977273 A few bug fixes and test updates 
- edge pairs are normalized before turning them into polygons.
  This makes flat and deep implementation more consistent.
- deep region and flat regions were not cooperating in geo
  checks
- unnamed layers are not registered in make_layer - this
  does not make sense and will just hold a fake ref
- tests now use GDS to represent texts after transformation
  (with orientation, OASIS can't do this)
- texts are more consistently handled in the tests
- test debug output is not written in the same format
  than golden data unless special normalization is
  requested.
- a non-orientable polygon was converted to orientable in
  a text because this can be represented in GDS consistently
- DRC testsuite uses "polygons" instead of "input" to achieve
  identical behavior for deep and flat mode with respect to
  texts
- dbRegionTests are updated because texts are not allowed
  for non-original layers too
 2019-03-09 19:40:38 +01:00
Matthias Koefferlein 8b29b30ff9 WIP: more consistent text handling 
Texts are not only kept inside original layers, but
also inside deep layers. This enables using texts
from DRC.

However, texts in deep layers are kept as markers.
Mostly they are converted back to texts, but the
orientation will be lost.

The change eliminates the need to using Iterators
in DRC instead of original layers and use of
label layers in deep mode.

A drawback is the presence of marker shapes in
deep mode (unless polygon layers are created).
Also, text output to RDB is not supported from
deep layers currently.
 2019-03-06 00:34:56 +01:00
Matthias Koefferlein 604a634bf1 Generalization of layout index for LayoutToNetlist 2019-03-03 18:10:52 +01:00
Matthias Koefferlein 261fb027fd GSI binding of antenna check function + tests. 2019-03-02 00:38:51 +01:00
Matthias Koefferlein 8d3b94201e Antenna check: tests added, 'catchall' diode protection 2019-03-01 23:07:28 +01:00
Matthias Koefferlein 9f4f2d58d7 First version of antenna check. 2019-02-28 23:56:49 +01:00
Matthias Koefferlein 4035c804b7 WIP: fixed bugs, added tests. 2019-02-28 22:23:20 +01:00
Matthias Koefferlein 36a3540e16 Allow empty regions for device extractor. 2019-02-25 23:51:21 +01:00
Matthias Koefferlein 21ea37f747 Updated test golden data. 2019-02-25 22:52:37 +01:00
Matthias Koefferlein 9b31bd3214 Fixed crash by introducing a new scheme for storing cluster refs 
The previous implementation was based on the Instance
pointers, but these got invalidated during device cell
construction. Now an explicit copy of the instance is
kept.
 2019-02-25 22:36:24 +01:00
Matthias Koefferlein d4ed21f42a Just new tests 2019-02-25 22:34:06 +01:00
Matthias Koefferlein 3c6aafcc0c Region: hierarchical text object detection implementated. 2019-02-23 00:56:55 +01:00
Matthias Koefferlein 18f74bac1e Enabled transformations for deep regions/edges/edge pairs - important for handling layouts with different DBUs in DRC 2019-02-22 01:02:48 +01:00
Matthias Koefferlein 91407ddaa9 Added tests for region processors. 2019-02-20 21:40:43 +01:00
Matthias Koefferlein 496b695ef0 Refactoring of the polygon processing in Region 2019-02-19 22:11:55 +01:00
Matthias Koefferlein 90c1d212a4 Refactoring: new concept for edge/polygon filters 2019-02-19 20:19:10 +01:00
Matthias Koefferlein 3918172c6a Fixed a nasty issue with editable mode. 2019-02-18 23:34:46 +01:00
Matthias Koefferlein 9ec6b44c93 Added some tests for the previous commit. 2019-02-18 00:15:26 +01:00
Matthias Koefferlein 311318c578 Ported edge/edge DRC functions to hierarchical mode. 2019-02-17 18:54:33 +01:00
Matthias Koefferlein c40f147dc7 Edge/edge and edge/polygon interaction test ported to hierarchical mode. 2019-02-17 18:36:15 +01:00
Matthias Koefferlein 7ef0451ca8 Partial segments of edges converted to hierarchical operations. 2019-02-17 17:53:21 +01:00
Matthias Koefferlein 74006b6208 Hierarchical implementation of extended method for edges 2019-02-17 17:34:31 +01:00
Matthias Koefferlein ae783a2245 Hiearchical implementation of edge filter. 2019-02-17 16:18:24 +01:00
Matthias Koefferlein 61d766bd4c Hierarchical implementation of edge to region operations. 2019-02-17 16:05:39 +01:00
Matthias Koefferlein e6ee1c064e Hierarchical implementation of edge/edge booleans. 2019-02-17 15:07:16 +01:00
Matthias Koefferlein 8e5bffcf18 Hierarchical angle check. 2019-02-17 11:42:30 +01:00
Matthias Koefferlein a7bfaac424 Cell variant resolution by propagation, grid check now implementation hierarchically (with propagation) 2019-02-17 10:59:04 +01:00
Matthias Koefferlein 5dc833970b Hierarchical implementation DRC functions (measurements) 2019-02-16 22:34:36 +01:00
Matthias Koefferlein 6e35e80963 Hierarchical implementation of polygon vs. edge interact 2019-02-15 23:43:45 +01:00
Matthias Koefferlein 78617930dd Hierarchical implementation of self-overlap merge. 2019-02-13 22:41:12 +01:00
Matthias Koefferlein ddcfda8761 Some optimization: keep merged state in deep region. 2019-02-13 17:17:03 +01:00
Matthias Koefferlein b0fc2be96e Deep regions: some more operations implemented hierarchically 
- snap (!) - but only for gx == gy
- filtering
- interact/inside/outside/overlap + not_... variants
- edges
 2019-02-13 01:07:32 +01:00
Matthias Koefferlein 10f9de8b66 Added test for edge-based clusters, edge connectivity modes 2019-02-12 22:14:50 +01:00
Matthias Koefferlein 4b5736ba6a Added result type template parameter to local hier processor. 2019-02-12 20:32:07 +01:00
Matthias Koefferlein 6404ca6b1d WIP: Deep edge pairs 2019-02-12 00:08:47 +01:00
Matthias Koefferlein 2d9a3aaaa6 WIP: Hierarchical production of error db's. Needs testing. 2019-02-11 00:11:03 +01:00
Matthias Koefferlein dd4fcd9e36 WIP: templatized local hierarchical processor. 2019-02-10 18:39:32 +01:00
Matthias Koefferlein a81a8cdbc8 Modified edge transformation to maintain the orientation paradigm 
When the transformation is mirroring, edges now swap their
points to maintain the right-is-inside paradigm.
 2019-02-10 16:03:46 +01:00
Matthias Koefferlein a14ca01bac WIP: more on deep edge collections. 2019-02-10 15:33:14 +01:00
Matthias Koefferlein 4abc38a5cc Test for deep/flat collaboration 2019-02-10 08:28:48 +01:00
Matthias Koefferlein e8e45b7272 Some tests, smooth and round method of deep region 2019-02-09 23:51:35 +01:00
Matthias Koefferlein 7a86f0d878 Bugfix: size method needs to produce polygon refs so the output is usable as input for booleans too. 2019-02-09 22:55:34 +01:00
Matthias Koefferlein b6dd149f53 Changed variant suffix to to be consistent with cell name suffix generation in KLayout. 2019-02-09 19:21:14 +01:00
Matthias Koefferlein 1f3af7bbfe Hierarchical area and perimeter and sizing 
Area and perimeter computation happens hierarchically
now. Magnified instances are supported.

Sizing is implemented hierarchically.

For anisotropic sizing, orientation variants may be
generated. For both isotropic and anisotropic
magnification variants will be created.
 2019-02-09 19:13:54 +01:00
Matthias Koefferlein bbf7b2768b WIP: cell variant collecting and building. 2019-02-09 16:29:34 +01:00
Matthias Koefferlein 50c8c067d5 WIP: cell variant formation utility class. 2019-02-07 23:13:23 +01:00
Matthias Koefferlein decc5ede13 Robustification of Region 
- Tests for merge
- Locking the layout when writing back the data for
  performance improvement
 2019-02-05 23:39:31 +01:00
Matthias Koefferlein 9c0123df20 Implemented implicit joining of nets with the same label. 2019-02-03 21:34:23 +01:00
Matthias Koefferlein c90f7e4af9 Introduced perimeter parameters for MOS3/MOS4 2019-02-02 01:29:28 +01:00
Matthias Koefferlein 4068478887 Implemented SPICE writer + tests. 2019-01-31 00:07:10 +01:00
Matthias Koefferlein 458d00969c Fixed issue #228 
Reason for the problem: the interaction test
has to keep separate "inside" records for both
below and above the scanline, not just once.
With the single record, the step in the
left polygon erased the "inside" condition.
 2019-01-27 00:04:15 +01:00
Matthias Koefferlein 29264013b0 WIP: more consistent handling of polygon splitting parameters. 2019-01-25 22:28:25 +01:00
Matthias Koefferlein 12aaa2db20 Refactoring: unified handling of splitting parameters. 2019-01-25 21:48:56 +01:00
Matthias Koefferlein 6da9bc5e85 Updated tests after switching to boolean core. 2019-01-25 21:38:45 +01:00
Matthias Koefferlein 707c761bac WIP: local hierarchical operations: take boolean core rather than shape ref core -> better hierarchical quality. Tests need to be fixed. 2019-01-25 00:21:01 +01:00
Matthias Koefferlein 1cfa3251ce Better reproducibility of results in hier processor: hash function of shape ref takes object hash, not pointer hash 2019-01-23 22:19:28 +01:00
Matthias Koefferlein 68fe668567 WIP: performance improvement. 2019-01-22 07:42:44 +01:00
Matthias Koefferlein 81bf47688e Renamed device model -> device abstract 2019-01-21 22:37:13 +01:00
Matthias Koefferlein d79a448eaa Some performance improvement by eliminating empty objects in the box scanner. 2019-01-21 22:37:02 +01:00
Matthias Koefferlein f83e1dae43 Refactoring, some bugfixes, GSI bindings for L2N methods. 2019-01-20 23:12:27 +01:00
Matthias Koefferlein 4c7f43d749 More l2n reader tests. 2019-01-20 17:31:58 +01:00
Matthias Koefferlein dd39168dc8 WIP: Enabled layout generation from read l2n data. 2019-01-20 02:50:23 +01:00
Matthias Koefferlein a5e2cf58c3 l2n dump format is leaner (device terminal shapes dropped from nets as they are contained in the device abstracts). Some refactoring. 2019-01-19 23:00:19 +01:00
Matthias Koefferlein 8213e71a79 WIP: l2n reader implementation, some bug fixes, refactoring. 2019-01-19 22:19:08 +01:00
Matthias Koefferlein 56bb39a273 LayoutToNetlist enhancements in the area of the dumper. 2019-01-16 22:45:58 +01:00
Matthias Koefferlein 438f50091f WIP: Refined output format for l2n 2019-01-16 00:49:51 +01:00
Matthias Koefferlein 4cb8982ca2 WIP: added concept of device model. 2019-01-15 23:03:25 +01:00
Matthias Koefferlein 5962d66940 WIP: major enhancements with respect to device handling 
The device handling in the netlist extractor was now
entirely moved to device cells. New options are introduced
for exporting these cells. Tests have been updated.
 2019-01-15 21:33:41 +01:00
Matthias Koefferlein 1af81b74d2 WIP: refactoring - turning devices into cells for better backannotation. 2019-01-14 00:59:47 +01:00
Matthias Koefferlein baf50bd0b1 WIP: refactoring - singularization of classes in separate files. 2019-01-10 23:36:52 +01:00
Matthias Koefferlein 9fa5618034 Added test for device combination. 2019-01-08 23:49:12 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein 294f1701b5 Added a test for joining of layers through multiple global net assignment. 2019-01-07 23:57:52 +01:00
Matthias Koefferlein 315bcdd016 WIP: bugfixed netlist extractor with global nets. 2019-01-07 23:33:57 +01:00
Matthias Koefferlein c80e335cd6 WIP: global nets integration in cluster builder. 2019-01-07 02:08:59 +01:00
Matthias Koefferlein a4f0fd665e Provided a solution for connectivity through global nets. 2019-01-06 17:50:51 +01:00