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607 Commits

Author SHA1 Message Date
Matthias Koefferlein 3f8113e404 WIP: Updated some test, debugging 2020-12-26 23:55:50 +01:00
Matthias Koefferlein dcaa0d0ea5 WIP: deep mode and complex DRC ops, debugging 2020-12-26 21:11:22 +01:00
Matthias Koefferlein 493024734d WIP: more tests enabled for deep mode 2020-12-26 20:48:11 +01:00
Matthias Koefferlein 1bb04c711c WIP: more tests enabled for deep mode too. 2020-12-26 19:55:42 +01:00
Matthias Koefferlein afc9fc9c7a WIP: Bugfixed deep processor (multi-input mode and input layer index), added tests 2020-12-26 19:43:51 +01:00
Matthias Koefferlein dc80ed77b1 WIP: region/edge booleans, more tests, debugging 2020-12-26 17:48:53 +01:00
Matthias Koefferlein 9b4f65bab4 Typo fixed 2020-12-26 17:18:23 +01:00
Matthias Koefferlein 953bee4790 WIP: more tests, debugging 2020-12-26 17:17:43 +01:00
Matthias Koefferlein 8d6dd23850 WIP: more tests, debugging 2020-12-26 17:06:44 +01:00
Matthias Koefferlein cc6ad01529 WIP: more tests, debugging 2020-12-26 16:04:35 +01:00
Matthias Koefferlein 00a7021a30 WIP: more tests, debugging. 2020-12-26 15:41:20 +01:00
Matthias Koefferlein 3707fae3c2 WIP: more tests, debugging 2020-12-26 14:58:07 +01:00
Matthias Koefferlein 9c6e0129d9 WIP: debugging, test case for compound booleans 2020-12-26 00:06:49 +01:00
Matthias Koefferlein 80509c64e5 WIP: generalization of EdgePair/Edge/Polgyon processors, chained operations in compound ops. 2020-12-25 18:03:57 +01:00
Matthias Koefferlein 4974a81af6 WIP: debugging 2020-12-25 15:00:52 +01:00
Matthias Koefferlein 45a8f7aa20 Merge branch 'master' into complex_drc_ops 2020-12-20 23:50:54 +01:00
Matthias Koefferlein 1c6ffb4086 Fixed unit tests. 2020-12-20 21:45:55 +01:00
Matthias Koefferlein db19e92083 Fixed some merge issues. 2020-12-20 20:53:43 +01:00
Matthias Koefferlein cfe38aab42 Merge branch 'lefdef' 2020-12-20 19:26:51 +01:00
Matthias Koefferlein 02f96f022a WIP: added brackets for clarity in mapping expressions. 2020-12-19 16:37:58 +01:00
Matthias Koefferlein 3fbfb20727 WIP: shorter mapping strings. 2020-12-19 00:56:45 +01:00
Matthias Koefferlein 3e249b0b54 WIP: More tests for layer multi-mapping 2020-12-15 23:51:01 +01:00
Matthias Koefferlein 1f635015ce WIP: backward compatible implementation of multi-map capability of layer mapping. 2020-12-15 23:05:34 +01:00
Matthias Koefferlein 86e7fa56f0 WIP: undo/redo for applying a technology. 2020-12-13 22:02:19 +01:00
Matthias Koefferlein fcf4fd74f6 WIP: bugfixing. 2020-12-13 14:13:59 +01:00
Matthias Koefferlein 78695f9c23 WIP: new technology management scheme, libraries can be tech specific, update of technology in layout updates library references 2020-12-13 12:13:21 +01:00
Matthias Koefferlein 57a7671640 Fixed enclosing feature, added tests + DRC impl., DRC doc. 2020-12-08 22:44:33 +01:00
Matthias Koefferlein 0670e83d77 WIP: bug fixes, renamed "enclosing" to "covering" in Region/DRC. 
Reasoning: "enclosing" was reserved for the DRC function.
 2020-12-07 23:55:52 +01:00
Matthias Koefferlein 153289b5d8 WIP: rectangle error pattern filter implemented. 2020-12-06 16:33:10 +01:00
Matthias Koefferlein 6c4d1f4ef3 WIP: bugfix and tests for opposite filter for DRC 2020-12-06 10:56:56 +01:00
Matthias Koefferlein 44fd6bff11 Refactoring: bulk options structure for DRC functions. Will be easer to enhance 2020-12-05 14:14:28 +01:00
Matthias Koefferlein db6b3d280e Merge branch 'master' into complex_drc_ops 2020-11-22 09:31:15 +01:00
Matthias Köfferlein 248168ea67
Merge pull request #677 from KLayout/issue-666 
Issue 666
 2020-11-14 20:55:28 +01:00
Matthias Köfferlein 94b71cbf76
Merge pull request #642 from KLayout/2.5d-view-devel 
2.5d view devel
 2020-11-13 02:06:41 +01:00
Matthias Koefferlein 888b0936f7 Updated test golden data (order of cells only) 2020-11-03 23:11:07 +01:00
Matthias Koefferlein 50ee44b6e2 Addressed issue #663 by internal merging of the intruders. 2020-10-28 23:01:54 +01:00
Matthias Koefferlein f1c7e2e8e1 Refactoring of the containers (Edges, Region, EdgePairs, Texts): size -> count, added hier_count. Added SRegion for shape iterator as generic polygonizable things 2020-10-11 17:51:54 +02:00
Matthias Köfferlein 591d4a5c37
Fixed #652 (M scaling not working sometimes for Spice), provided test… (#653) 
* Fixed #652 (M scaling not working sometimes for Spice), provided testcases

* One more patch (bugfix, Spice reader)
 2020-10-10 23:16:02 +02:00
Matthias Köfferlein 52f54ab39e
Fixed #648 (join_nets should work on global nets too) (#655) 2020-10-10 23:15:36 +02:00
Matthias Koefferlein ec01c9b72b WIP: tests for local processor flat mode 2020-09-26 17:11:13 +02:00
Matthias Koefferlein 91e924c559 WIP: Basic implementation of Region::interact with count 2020-09-21 22:54:46 +02:00
Matthias Koefferlein ce9c7e848a Merge branch 'master' into drc-enhancements 2020-09-14 20:52:02 +02:00
Matthias Koefferlein b5e158a6b6 Merge branch 'master' into 2.5d-view-devel 2020-09-14 20:48:46 +02:00
Matthias Koefferlein 1dc9d11745 Merge branch 'master' into 2.5d-view-devel 2020-08-30 23:40:54 +02:00
Matthias Koefferlein 2953ad3329 Merge branch 'master' into drc-enhancements 2020-08-30 23:35:37 +02:00
Matthias Koefferlein a425d522cc Added multi-cell mapping for transferring multiple cells from one layout to another while including their hierarchy without duplicating cells. 2020-08-29 10:07:17 +02:00
Matthias Koefferlein 4d4c7aee78 Fixed a unit test. 2020-07-17 23:59:37 +02:00
Matthias Koefferlein 0dbebdca91 Fixed test. 2020-07-07 21:39:24 +02:00
Matthias Koefferlein 848fd3e1bb Added testcase 2020-07-07 21:21:33 +02:00
Matthias Köfferlein dcd0476efc
Implemented issue #598 (Cell#transform) (#600) 2020-07-03 23:41:09 +02:00
Matthias Köfferlein 4bd2672134
Fixed #592 (layer mapping issue) (#601) 2020-07-03 23:40:55 +02:00
Matthias Köfferlein b413cb9d74
Netlist compare: Ambiguity resolution through name matching now default (can be turned off) (#594) 
* WIP: some refactoring

* WIP: some refactoring

* Netlist compare: introducing ambiguity resolution by net names

By default now net names are used for resolving ambiguities.
If net names match, they will be used to associate nets if the
choice is ambiguous. This is usually much faster and more reliable
than trying to resolve ambiguities through topology analysis.

This feature can be disabled using "consider_net_names(false)" in
the LVS script.

* Some refactoring, Jenkinsfile modified for better test coverage
 2020-06-29 20:47:57 +02:00
Matthias Köfferlein e744eb32d1
Merge pull request #580 from KLayout/drawing-performance2 
Drawing performance2
 2020-06-28 16:14:48 +02:00
Matthias Koefferlein c517aa4ff7 Cherry-picked MacOS fixes into master 2020-06-27 01:47:35 +02:00
Matthias Koefferlein b91e2324d0 Netlist compare enhancement 
This enhancement targets towards a better resolution
of ambiguities. The enhancement is to utilize knowledge
about device and subcircuit equivalences to avoid stale
branches of the ambiguity resolution tree.

So far following these branches could lead to a
contradictions which render an ambiguitiy resolution
choice useless.

One effect of this change is enhanced reproducibility
of the matching log because some pointers are not
involved anymore.
 2020-06-26 17:01:03 +02:00
Matthias Koefferlein d141c0895d Added tests for Region's andnot. 2020-06-14 18:12:17 +02:00
Matthias Koefferlein 3637b15a74 Generalization of code for twobool local operation 2020-06-14 17:06:53 +02:00
Matthias Koefferlein 41fe04bbc8 WIP: twobool local processor 2020-06-14 17:00:54 +02:00
Matthias Koefferlein 041abe3e89 Added a testcase for two-boolean edge processor. 2020-06-14 16:50:34 +02:00
Matthias Koefferlein 4390a80dda Added test cases for multiple-outputs local processors. 2020-06-13 23:57:40 +02:00
Matthias Koefferlein 96caa646f5 WIP: preparations for multi-input/multi-output local processor. 2020-06-07 18:04:30 +02:00
Matthias Köfferlein 2d0a9418f9
Implemented #579 (perimeter_only mode for antenna check) (#582) 
* WIP: added basic feature and tests.

* WIP: provide tests are GSI binding of new antenna check

* Fixed issue #579 (perimeter_only mode for antenna check)

* Updated DRC doc for 'perimeter_only'
 2020-06-05 10:55:07 +02:00
Matthias Koefferlein 999c065262 Introducing iterated arrays for instances 
Iterated instances are created for OASIS files
using irregular repetitions in viewer mode.

Reason: this way, the same drawing optimization
than for iterated shape arrays can be applied.

As this is a new API feature, some adjustments
had to be made to incorporate them into the
code.
 2020-06-04 12:17:34 +02:00
Matthias Koefferlein cdf4d08fd3 WIP 
* Maybe fixed a performance issue on box-trees: the iterator wasn't
  going down to the very bottom of the tree on initialization
* Added array quad skipping in display of shape arrays
 2020-06-01 23:28:04 +02:00
Matthias Koefferlein 759f07ee4d Implemented solution for #570 (deep Edges::extents) 
While doing this, it was discovered that the problem also
persists for EdgePairs and Texts.

In order to provide a more generic solution, some refactoring
was applied.
 2020-05-31 01:55:05 +02:00
Matthias Köfferlein 6601d472bf
Implemented #570 (perimeter included in antenna check) (#572) 
* First implementation of the perimeter factor for antenna check, unit tests.

* Bugfix and unit tests for GSI binding of new antenna check version.

* DRC integration of perimeter-enabled antenna check.

* Enhanced DRC doc for antenna rule
 2020-05-30 21:45:48 +02:00
Matthias Köfferlein 3246e0d36f
Fixed #565 (SPICE global nets must not produce pins if not present) (#567) 
* Fixed #565 (SPICE global nets must not produce pins if not present)

* Fixed unit tests.
 2020-05-26 23:47:59 +02:00
Matthias Koefferlein 5ba3d220e9 Made unit tests a little more consistent. 2020-05-23 22:30:54 +02:00
Matthias Koefferlein b84a9df2da Persisting texts now for .l2n format 2020-05-22 00:58:46 +02:00
Matthias Koefferlein c682cc85d0 Generalized concept of region, texts etc. into 'shape collections'. Fixed LVS and DRC tests. 2020-05-21 23:59:30 +02:00
Matthias Koefferlein 854320d52d Debugging: proper assignment of net names through labels. 2020-05-20 23:27:06 +02:00
Matthias Koefferlein e9af72ee28 Tests for texts as net names, fixed Shapes test (order of texts) 2020-05-20 01:05:19 +02:00
Matthias Koefferlein 4c13bb96a0 WIP: refactoring - texts for net extractor. 2020-05-20 00:21:06 +02:00
Matthias Koefferlein 7dab87b881 Added tests, Region#pull_interacting with texts 2020-05-15 23:48:21 +02:00
Matthias Koefferlein 831acb2c40 Bugfixes, tests for flat interact between region and texts. 2020-05-13 18:25:43 +02:00
Matthias Koefferlein 16d6c75b0e Fixed build, added tests for filter in deep texts object. 2020-05-13 17:58:00 +02:00
Matthias Koefferlein 4e7d0a81b8 'interact' between regions and texts. 2020-05-13 17:29:10 +02:00
Matthias Koefferlein c1b1ce6951 Provide unit test for DeepTexts. 2020-05-12 21:43:11 +02:00
Matthias Koefferlein 4fbb6286ac Fixed unit tests. 2020-05-12 21:16:12 +02:00
Matthias Koefferlein 8b083a8330 Added unit tests for db::Texts, renamed db unit test files so debugging is possible 2020-05-12 21:09:21 +02:00
Matthias Köfferlein cb3833f563
Merge pull request #546 from KLayout/sonarqube-fixes 
Sonarqube fixes
 2020-04-30 22:06:38 +02:00
Matthias Köfferlein 9b0362d03d
Fixed #544 (ignore duplicate global nets in SPICE reader) (#545) 2020-04-26 16:54:13 +02:00
Matthias Köfferlein 93a072903c
Fixed #539 (internal error on circuit flatten) (#542) 
Previously, circuits which connected two pins through
a net could not be flattened. This capability now has
been added.
 2020-04-26 16:53:50 +02:00
Matthias Koefferlein 73f2f23505 Adjusted unit tests for latest fix. 2020-04-26 01:05:07 +02:00
Matthias Koefferlein 2cdcf621d8 D25 tech component editor: line numbers shown, more syntax variants 2020-04-18 00:37:15 +02:00
Matthias Koefferlein ca2b0cd96a Added tests for tech component, syntax highlighter fixed. 2020-04-17 16:24:56 +02:00
Matthias Köfferlein c93db59e37
Fixed #524 (failed query leaves layout in invalid state) (#528) 2020-04-05 15:11:37 +02:00
Matthias Koefferlein c640347570 MERGE: added Spice reader testcase for resistors with model names. 2020-04-01 23:19:21 +02:00
Matthias Koefferlein c021d60d41 Updated unit test 2020-03-29 09:23:13 +02:00
Matthias Koefferlein 99d3610a6a Implemented #527 (wildcard layer mapping targets) 
commit d77702cd86066f3a97d740a95923fa598c2ff07b
Author: Matthias Koefferlein <matthias@koefferlein.de>
Date:   Sat Mar 28 21:28:39 2020 +0100

    Wildcard expansion feature on layer mapping

    Finished feature, added doc and test.

    The solution is to use placeholder indexes for the
    layer mapping which are substituted by the real
    layers when they are encountered.

commit af60b5f18acfe3c5e2f1d4e6bc6ee752a246dc0d
Author: Matthias Koefferlein <matthias@koefferlein.de>
Date:   Sat Mar 28 19:11:32 2020 +0100

    Preparations for new feature: introduce relative and wildcard target layer specs
 2020-03-28 22:49:57 +01:00
Matthias Koefferlein a47932a79e Added one more testcase for join_symmetric_nets 2020-03-28 09:49:41 +01:00
Matthias Koefferlein c10ccccdf7 Merge branch 'app-refactoring' into doc-args 2020-03-15 21:32:39 +01:00
Matthias Koefferlein a5a4ae511d Some more tests, a (unlikely) segfault fixed 2020-02-28 23:19:27 +01:00
Matthias Koefferlein 75e936bd64 Added one more test case. 2020-02-27 13:46:52 +01:00
Matthias Koefferlein 3b31109367 Added GSI binding for join_symmetric_nets, added method to get circuits by name pattern. 2020-02-27 12:17:35 +01:00
Matthias Koefferlein a46cd305c6 WIP: bug fix for symmetry detection (should consider different pins to break symmetry). Added tests. 2020-02-27 00:52:06 +01:00
Matthias Koefferlein b35429291e WIP: join_nets implemented, join_symmetric_nets: enhanced detection of symmetric nets. 2020-02-27 00:52:03 +01:00
Matthias Koefferlein 08af8d85c4 WIP: first algorithm - is capable of deriving the 'resistor cube' symmetry. 2020-02-27 00:52:00 +01:00
Matthias Koefferlein 0f69c24e79 WIP: avoids a segfault because of missing manager 2020-02-04 20:50:46 +01:00
Matthias Köfferlein 6a996b6f5b
Merge pull request #465 from KLayout/issue-462 
Implemented #462 (Generalize MOS transistor extraction to other gate …
 2020-01-05 01:02:54 +01:00
Matthias Koefferlein b8c82c4f8b Updated copyright notice to 2020 2020-01-05 00:59:43 +01:00
Matthias Koefferlein 811560094a Updated tests. 2020-01-04 21:19:06 +01:00
Matthias Koefferlein 833edf53b2 Implemented #462 (Generalize MOS transistor extraction to other gate figures) 2020-01-02 22:20:45 +01:00
Matthias Koefferlein c4636cebdb Fixed #458 (Array instance net tracing bug) 2019-12-23 20:38:17 +01:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein da1ac3661f WIP: bugfix of refactoriung, update test data. 2019-12-15 00:16:47 +01:00
Matthias Koefferlein 4acc4b96e2 First attempt to fix the issue 
Problem was caching which did not take into account the array nature
of instances.

This fix also moves the cache one level below so it is effective also
when instance tree traversal happens. This might speed up things too.

Needs testing.
 2019-12-09 21:37:07 +01:00
Matthias Koefferlein 3b9beb0d49 Fixed #438 (error on redefinition of subcircuit in SPICE) 2019-12-07 23:39:39 +01:00
Matthias Koefferlein 0f1dc1d191 Refine pin mismatch handling so that only 'not used' nets will make a pin match against null. 2019-11-24 16:40:45 +01:00
Matthias Koefferlein aa28aa807a Unit tests fixed and a bugfix in the netlist compare 
One unit test was failing because the netlist compare did not
properly consider dropped pins:
* A severe bug ("g1" should be "g2")
* Incomplete detection of dropped pins upwards in the hierarchy

The general pin and net mapping scheme has been enhanced so that
net mapping to "0" is valid (this will happen in case of dropped
pins) and this condition is used to detect pins without match
requirement.
 2019-11-23 22:04:25 +01:00
Matthias Koefferlein 1309aa59cb Merge branch 'master' into issue-425 2019-11-23 01:55:28 +01:00
Matthias Koefferlein 7de90ae595 Merge branch 'issue-417' 2019-11-23 01:46:38 +01:00
Matthias Koefferlein 79f4f8bc57 Update unit test for issue-417 branch. 2019-11-23 01:45:56 +01:00
Matthias Koefferlein d5506a176a WIP: first implementation - needs testing. 2019-11-23 01:20:22 +01:00
Matthias Koefferlein 2757b22da6 Resolved conflicts for issue-419 merge 2019-11-22 23:34:03 +01:00
Matthias Köfferlein a792cf4c1e
Merge pull request #424 from KLayout/issue-407 
Issue 407
 2019-11-22 23:12:44 +01:00
Matthias Köfferlein ac7e17ffcb
Merge pull request #422 from KLayout/issue-406 
Issue 406
 2019-11-22 23:12:16 +01:00
Matthias Köfferlein c8cf8122b6
Merge pull request #414 from KLayout/issue-411 
Issue 411
 2019-11-22 23:11:24 +01:00
Matthias Koefferlein 247bfa9ac5 Implemented #407 (variables in technology base path) 
The implementation uses extrapolation of strings in the
"Expressions" framework.

There is how:
* $(tech_name) -> substituted by the technology name
* $(tech_dir) -> substituted by the directory the technology file is stored in
* $(tech_file) -> substituted by the absolute path to the tech file
* $(appdata_path) -> substituted by KLayout's home directory (e.g. ~/.klayout)
* $(env('X')) -> substituted by the environment variable $X
 2019-11-21 21:37:00 +01:00
Matthias Koefferlein 6648b53822 Fixed issue #419 (multiple top circuits after flatten of netlist) 
The problem is solved by always producing subcircuits for cell
instances, even if there are no connections.

The netlist comparer had to be adjusted too because subcircuits
without pins were used for representing "unknown" subcircuit pairing.

In addition, this patch should lead to a better matching of
parallel subcircuit configurations where two different subcircuits
are entirely parallel.
 2019-11-20 21:56:12 +01:00
Matthias Koefferlein 6c7ceb74dc Enhanced intersections algorithm so that the generated points won't overlay with finite edges from the AND part 2019-11-19 21:19:36 +01:00
Matthias Koefferlein 9af662a512 WIP: try to avoid duplicate intersection points by eliminating those. Problem persists: intersection points may be duplicates of edges arising from AND 2019-11-18 23:14:24 +01:00
Matthias Koefferlein 990961e5f4 Fixed #411 (multiple device extractors for same class) 2019-11-17 23:12:50 +01:00
Matthias Koefferlein 8dddc4000f Also write the net properties to GDS or OASIS 
"build_nets" will now write the net's properties
to the generated net shapes.
This might enable interesting applications.
 2019-11-13 23:09:09 +01:00
Matthias Koefferlein bb3aed5773 Merge branch 'master' of https://github.com/KLayout/klayout into netlist_properties 2019-11-13 00:59:29 +01:00
Matthias Koefferlein 876487edde Added persistency of the netlist object properties into L2N/LVSDB files 2019-11-13 00:06:29 +01:00
Matthias Koefferlein d060147713 Enhancements for the netlist object properties 
- more memory efficient (single pointer only)
- iterator for properties
- NetlistObject#property_keys in GSI
 2019-11-12 23:00:49 +01:00
Matthias Koefferlein 86e041cd51 Updated test data. 2019-11-11 23:03:40 +01:00
Matthias Koefferlein 0ce06125ca Introducing netlist object properties. 2019-11-11 07:02:02 +01:00
Matthias Koefferlein 4a212e8db6 Added tests for Region#scale_and_snap and Region#snap 2019-11-07 23:33:54 +01:00
Matthias Koefferlein 988b1e563f Added unit test for DeepRegion::snap 2019-11-07 23:11:34 +01:00
Matthias Koefferlein 318efbf7b0 Fixed 'scale_and_snap' feature 2019-11-07 22:54:16 +01:00
Matthias Koefferlein 4924d0269c Fixed #400, added tests. 2019-11-06 23:28:16 +01:00
Matthias Koefferlein 3cc38fcfc2 Solved ambiguous bus resolution problem. 2019-10-29 23:26:17 +01:00
Matthias Koefferlein 15fa99c128 WIP: bugfix ambiguous bus-like pins and net compare. 2019-10-29 22:53:37 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein 373a3db1ec WIP: netlist comparer - increase default depth and added test 
The test is specific for symmetric circuits with manifold
symmetry axes.
 2019-10-24 23:58:30 +02:00
Matthias Koefferlein ac479c30bc Fixed unit tests. 2019-10-24 00:23:03 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein 611f62e73f Removed debug leftover code 2019-10-17 22:47:43 +02:00
Matthias Koefferlein 2325e1bce4 Merge branch 'dvb' into pull_feature 2019-10-04 22:58:52 +02:00
Matthias Koefferlein ef56264f64 Fixed a regular arrays issue with begin_touching 
In case of 1d arrays with a or b == (0,0), the iterator
was always delivering all items, not just the touching ones.
 2019-10-04 22:45:23 +02:00
Matthias Koefferlein 5ed41cc345 Merge branch 'master' into pull_feature 2019-10-03 14:32:25 +02:00
Matthias Koefferlein e1d77a1476 pull_interacting for edges/edges and edges/regions, some enhancements and bug fixes 
Bug fixes:
- use dist 1 to cover touching case properly in local processor
- handling of raw mode and is_merged state

Additional tests
 2019-10-03 13:08:37 +02:00
Matthias Koefferlein 76b8bd3279 Fixed several issues with raw mode/merged semantics and many Region and Edges methods. Added edge/edge pull and edge/polygon pull. 2019-10-03 01:46:49 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 506cfc1c6f WIP: attempt to retain nets which don't have active elements but pins. This is supposed to simplify debugging in case of fake pins. When removing those nets, the pin is very difficult to find. 2019-09-30 20:58:55 +02:00
Matthias Koefferlein d69c60a5c5 Enabled net tracing for heavily decomposed polygons 2019-09-19 00:13:14 +02:00
Matthias Koefferlein 56084b6b59 Merge branch 'dvb' 2019-09-08 20:07:16 +02:00
Matthias Koefferlein e2cc0c48b1 Provide flat and hierarchical 'trace all nets' feature, added Netlist#flatten. 2019-09-06 23:13:21 +02:00