mirror of https://github.com/KLayout/klayout.git
Updated tests.
This commit is contained in:
Matthias Koefferlein
parent
d7eb9162ce
commit
2d4f23abd1
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@ -486,67 +486,7 @@ static std::string pin2string (const db::Pin &pin)
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}
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}
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std::string Netlist::to_string_old () const
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{
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std::string res;
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for (db::Netlist::const_circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) {
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std::string ps;
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for (db::Circuit::const_pin_iterator p = c->begin_pins (); p != c->end_pins (); ++p) {
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if (! ps.empty ()) {
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ps += ",";
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}
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ps += pin2string (*p) + "=" + net2string (c->net_for_pin (p->id ()));
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}
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res += std::string ("Circuit ") + c->name () + " (" + ps + "):\n";
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#if 0 // for debugging
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for (db::Circuit::const_net_iterator n = c->begin_nets (); n != c->end_nets (); ++n) {
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res += " N" + net_name (n.operator-> ()) + " pins=" + tl::to_string (n->pin_count ()) + " sc_pins=" + tl::to_string (n->subcircuit_pin_count ()) + " terminals=" + tl::to_string (n->terminal_count ()) + "\n";
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}
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#endif
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for (db::Circuit::const_device_iterator d = c->begin_devices (); d != c->end_devices (); ++d) {
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std::string ts;
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const std::vector<db::DeviceTerminalDefinition> &td = d->device_class ()->terminal_definitions ();
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for (std::vector<db::DeviceTerminalDefinition>::const_iterator t = td.begin (); t != td.end (); ++t) {
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if (t != td.begin ()) {
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ts += ",";
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}
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ts += t->name () + "=" + net2string (d->net_for_terminal (t->id ()));
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}
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std::string ps;
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const std::vector<db::DeviceParameterDefinition> &pd = d->device_class ()->parameter_definitions ();
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for (std::vector<db::DeviceParameterDefinition>::const_iterator p = pd.begin (); p != pd.end (); ++p) {
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if (p != pd.begin ()) {
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ps += ",";
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}
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ps += p->name () + "=" + tl::to_string (d->parameter_value (p->id ()));
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}
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res += std::string (" D") + d->device_class ()->name () + " " + device2string (*d) + " (" + ts + ") [" + ps + "]\n";
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}
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for (db::Circuit::const_subcircuit_iterator sc = c->begin_subcircuits (); sc != c->end_subcircuits (); ++sc) {
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std::string ps;
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const db::SubCircuit &subcircuit = *sc;
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const db::Circuit *circuit = sc->circuit_ref ();
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for (db::Circuit::const_pin_iterator p = circuit->begin_pins (); p != circuit->end_pins (); ++p) {
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if (p != circuit->begin_pins ()) {
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ps += ",";
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}
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const db::Pin &pin = *p;
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ps += pin2string (pin) + "=" + net2string (subcircuit.net_for_pin (pin.id ()));
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}
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res += std::string (" X") + circuit->name () + " " + subcircuit2string (*sc) + " (" + ps + ")\n";
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}
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}
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return res;
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}
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std::string Netlist::to_parsable_string () const
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std::string Netlist::to_string () const
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{
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std::string res;
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for (db::Netlist::const_circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) {
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@ -87,19 +87,12 @@ public:
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*/
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void clear ();
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/**
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* @brief Returns a string representation of the netlist
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*
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* This method is basically intended to testing.
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*/
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std::string to_string_old () const;
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/**
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* @brief Returns a parsable string representation of the netlist
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*
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* This method returns a string suitable for being put into from_string.
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*/
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std::string to_parsable_string () const;
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std::string to_string () const;
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/**
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* @brief Reads a netlist from the string generated by to_parsable_string
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@ -972,7 +972,7 @@ Class<db::Netlist> decl_dbNetlist ("db", "Netlist",
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gsi::iterator ("each_device_class", (db::Netlist::device_class_iterator (db::Netlist::*) ()) &db::Netlist::begin_device_classes, (db::Netlist::device_class_iterator (db::Netlist::*) ()) &db::Netlist::end_device_classes,
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"@brief Iterates over the device classes of the netlist"
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) +
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gsi::method ("to_s", &db::Netlist::to_parsable_string,
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gsi::method ("to_s", &db::Netlist::to_string,
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"@brief Converts the netlist to a string representation.\n"
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"This method is intended for test purposes mainly."
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) +
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@ -337,7 +337,7 @@ TEST(1_BasicExtraction)
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db::compare_layouts (_this, ly, au);
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO ();\n"
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" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n"
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@ -495,7 +495,7 @@ TEST(1_BasicExtraction)
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l2n.netlist ()->purge ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n"
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" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD);\n"
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@ -689,7 +689,7 @@ TEST(2_Probing)
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dump_recursive_nets_to_layout (l2n, ly, dump_map, cm);
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO ();\n"
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" subcircuit INV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC);\n"
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" subcircuit INV2PAIR $2 ($1=$I18,$2=VDD,$3=VSS,$4=FB,$5=$I9);\n"
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@ -745,7 +745,7 @@ TEST(2_Probing)
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l2n.netlist ()->purge ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n"
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" subcircuit INV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC);\n"
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" subcircuit INV2PAIR $2 ($1=(null),$2=VDD,$3=VSS,$4=FB,$5=$I9);\n"
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@ -968,7 +968,7 @@ TEST(3_GlobalNetConnections)
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dump_recursive_nets_to_layout (l2n, ly, dump_map, cm);
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO ();\n"
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" subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n"
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" subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n"
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@ -1024,7 +1024,7 @@ TEST(3_GlobalNetConnections)
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l2n.netlist ()->purge ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');\n"
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" subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n"
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" subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n"
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@ -1253,7 +1253,7 @@ TEST(4_GlobalNetDeviceExtraction)
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dump_recursive_nets_to_layout (l2n, ly, dump_map, cm);
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO ();\n"
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" subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n"
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" subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n"
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@ -1309,7 +1309,7 @@ TEST(4_GlobalNetDeviceExtraction)
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l2n.netlist ()->purge ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');\n"
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" subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n"
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" subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n"
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@ -1538,7 +1538,7 @@ TEST(5_DeviceExtractionWithDeviceCombination)
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dump_recursive_nets_to_layout (l2n, ly, dump_map, cm);
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO ();\n"
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" subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=FB,$5=$I7,$6=OSC,$7=VDD);\n"
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" subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I22,$5=FB,$6=$I13,$7=VDD);\n"
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@ -1591,7 +1591,7 @@ TEST(5_DeviceExtractionWithDeviceCombination)
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l2n.netlist ()->purge ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');\n"
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" subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=FB,$5=$I7,$6=OSC,$7=VDD);\n"
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" subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=FB,$6=$I13,$7=VDD);\n"
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@ -1765,7 +1765,7 @@ TEST(6_MoreDeviceTypes)
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l2n.extract_netlist ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit TOP ();\n"
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" device HVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n"
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" device HVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n"
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@ -1921,7 +1921,7 @@ TEST(7_MoreByEmptyDeviceTypes)
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l2n.extract_netlist ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit TOP ();\n"
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" device LVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n"
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" device LVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n"
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@ -2099,7 +2099,7 @@ TEST(8_FlatExtraction)
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l2n.extract_netlist ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit TOP ();\n"
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" device HVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n"
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" device HVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n"
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@ -2282,7 +2282,7 @@ TEST(9_FlatExtractionWithExternalDSS)
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l2n.extract_netlist ();
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// compare netlist as string
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EXPECT_EQ (l2n.netlist ()->to_parsable_string (),
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EXPECT_EQ (l2n.netlist ()->to_string (),
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"circuit TOP ();\n"
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" device LVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n"
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" device LVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n"
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@ -64,7 +64,7 @@ TEST(1_SerialResistors)
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r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3);
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circuit->connect_pin (pin_b.id (), n3);
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n1,B=n2) (R=1);\n"
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" device '' r2 (A=n2,B=n3) (R=3);\n"
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@ -74,7 +74,7 @@ TEST(1_SerialResistors)
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nl.combine_devices ();
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nl.purge ();
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n1,B=n3) (R=4);\n"
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"end;\n"
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@ -117,7 +117,7 @@ TEST(2_SerialResistors1Swapped)
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r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n3);
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circuit->connect_pin (pin_b.id (), n3);
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n1,B=n2) (R=1);\n"
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" device '' r2 (A=n3,B=n2) (R=3);\n"
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@ -127,7 +127,7 @@ TEST(2_SerialResistors1Swapped)
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nl.combine_devices ();
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nl.purge ();
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n1,B=n3) (R=4);\n"
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"end;\n"
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@ -170,7 +170,7 @@ TEST(3_SerialResistors1OtherSwapped)
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r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3);
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circuit->connect_pin (pin_b.id (), n3);
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n2,B=n1) (R=1);\n"
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" device '' r2 (A=n2,B=n3) (R=3);\n"
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@ -180,7 +180,7 @@ TEST(3_SerialResistors1OtherSwapped)
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nl.combine_devices ();
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nl.purge ();
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n3,B=n1) (R=4);\n"
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"end;\n"
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@ -223,7 +223,7 @@ TEST(4_SerialResistors2Swapped)
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r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n3);
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circuit->connect_pin (pin_b.id (), n3);
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n2,B=n1) (R=1);\n"
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" device '' r2 (A=n3,B=n2) (R=3);\n"
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@ -233,7 +233,7 @@ TEST(4_SerialResistors2Swapped)
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nl.combine_devices ();
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nl.purge ();
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3);\n"
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" device '' r1 (A=n3,B=n1) (R=4);\n"
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"end;\n"
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@ -278,7 +278,7 @@ TEST(5_SerialResistorsNoCombination)
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r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3);
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circuit->connect_pin (pin_b.id (), n3);
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EXPECT_EQ (nl.to_parsable_string (),
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n3,C=n2);\n"
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" device '' r1 (A=n1,B=n2) (R=1);\n"
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" device '' r2 (A=n2,B=n3) (R=3);\n"
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@ -288,7 +288,7 @@ TEST(5_SerialResistorsNoCombination)
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nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3,C=n2);\n"
|
||||
" device '' r1 (A=n1,B=n2) (R=1);\n"
|
||||
" device '' r2 (A=n2,B=n3) (R=3);\n"
|
||||
|
|
@ -329,7 +329,7 @@ TEST(6_ParallelResistors)
|
|||
r1->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2);
|
||||
r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n1,B=n2) (R=2);\n"
|
||||
" device '' r2 (A=n1,B=n2) (R=3);\n"
|
||||
|
|
@ -339,7 +339,7 @@ TEST(6_ParallelResistors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n1,B=n2) (R=1.2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -379,7 +379,7 @@ TEST(7_ParallelResistors1Swapped)
|
|||
r1->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2);
|
||||
r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n2,B=n1) (R=2);\n"
|
||||
" device '' r2 (A=n1,B=n2) (R=3);\n"
|
||||
|
|
@ -389,7 +389,7 @@ TEST(7_ParallelResistors1Swapped)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n2,B=n1) (R=1.2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -429,7 +429,7 @@ TEST(8_ParallelResistors1OtherSwapped)
|
|||
r1->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2);
|
||||
r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n1,B=n2) (R=2);\n"
|
||||
" device '' r2 (A=n2,B=n1) (R=3);\n"
|
||||
|
|
@ -439,7 +439,7 @@ TEST(8_ParallelResistors1OtherSwapped)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n1,B=n2) (R=1.2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -479,7 +479,7 @@ TEST(9_ParallelResistors2Swapped)
|
|||
r1->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2);
|
||||
r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n2,B=n1) (R=2);\n"
|
||||
" device '' r2 (A=n2,B=n1) (R=3);\n"
|
||||
|
|
@ -489,7 +489,7 @@ TEST(9_ParallelResistors2Swapped)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' r1 (A=n2,B=n1) (R=1.2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -554,7 +554,7 @@ TEST(10_ComplexRegistorCombination)
|
|||
circuit->connect_pin (pin_b.id (), n4);
|
||||
r4->connect_terminal (db::DeviceClassResistor::terminal_id_B, n4);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n4);\n"
|
||||
" device '' r1 (A=n1,B=n2) (R=1);\n"
|
||||
" device '' r2 (A=n2,B=n3) (R=1);\n"
|
||||
|
|
@ -566,7 +566,7 @@ TEST(10_ComplexRegistorCombination)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n4);\n"
|
||||
" device '' r4 (A=n1,B=n4) (R=2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -609,7 +609,7 @@ TEST(11_SerialInductors)
|
|||
l2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3);
|
||||
circuit->connect_pin (pin_b.id (), n3);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3);\n"
|
||||
" device '' l1 (A=n1,B=n2) (L=1);\n"
|
||||
" device '' l2 (A=n2,B=n3) (L=3);\n"
|
||||
|
|
@ -619,7 +619,7 @@ TEST(11_SerialInductors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3);\n"
|
||||
" device '' l1 (A=n1,B=n3) (L=4);\n"
|
||||
"end;\n"
|
||||
|
|
@ -659,7 +659,7 @@ TEST(12_ParallelInductors)
|
|||
l1->connect_terminal (db::DeviceClassInductor::terminal_id_B, n2);
|
||||
l2->connect_terminal (db::DeviceClassInductor::terminal_id_B, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' l1 (A=n1,B=n2) (L=2);\n"
|
||||
" device '' l2 (A=n1,B=n2) (L=3);\n"
|
||||
|
|
@ -669,7 +669,7 @@ TEST(12_ParallelInductors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' l1 (A=n1,B=n2) (L=1.2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -712,7 +712,7 @@ TEST(13_SerialCapacitors)
|
|||
c2->connect_terminal (db::DeviceClassCapacitor::terminal_id_B, n3);
|
||||
circuit->connect_pin (pin_b.id (), n3);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3);\n"
|
||||
" device '' c1 (A=n1,B=n2) (C=2);\n"
|
||||
" device '' c2 (A=n2,B=n3) (C=3);\n"
|
||||
|
|
@ -722,7 +722,7 @@ TEST(13_SerialCapacitors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3);\n"
|
||||
" device '' c1 (A=n1,B=n3) (C=1.2);\n"
|
||||
"end;\n"
|
||||
|
|
@ -762,7 +762,7 @@ TEST(14_ParallelCapacitors)
|
|||
c1->connect_terminal (db::DeviceClassCapacitor::terminal_id_B, n2);
|
||||
c2->connect_terminal (db::DeviceClassCapacitor::terminal_id_B, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' c1 (A=n1,B=n2) (C=1);\n"
|
||||
" device '' c2 (A=n1,B=n2) (C=3);\n"
|
||||
|
|
@ -772,7 +772,7 @@ TEST(14_ParallelCapacitors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' c1 (A=n1,B=n2) (C=4);\n"
|
||||
"end;\n"
|
||||
|
|
@ -815,7 +815,7 @@ TEST(15_SerialDiodes)
|
|||
d2->connect_terminal (db::DeviceClassDiode::terminal_id_C, n3);
|
||||
circuit->connect_pin (pin_b.id (), n3);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3);\n"
|
||||
" device '' d1 (A=n1,C=n2) (A=2);\n"
|
||||
" device '' d2 (A=n2,C=n3) (A=3);\n"
|
||||
|
|
@ -827,7 +827,7 @@ TEST(15_SerialDiodes)
|
|||
|
||||
// serial diodes are not combined!
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n3);\n"
|
||||
" device '' d1 (A=n1,C=n2) (A=2);\n"
|
||||
" device '' d2 (A=n2,C=n3) (A=3);\n"
|
||||
|
|
@ -868,7 +868,7 @@ TEST(16_ParallelDiodes)
|
|||
d1->connect_terminal (db::DeviceClassDiode::terminal_id_C, n2);
|
||||
d2->connect_terminal (db::DeviceClassDiode::terminal_id_C, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' d1 (A=n1,C=n2) (A=1);\n"
|
||||
" device '' d2 (A=n1,C=n2) (A=3);\n"
|
||||
|
|
@ -878,7 +878,7 @@ TEST(16_ParallelDiodes)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' d1 (A=n1,C=n2) (A=4);\n"
|
||||
"end;\n"
|
||||
|
|
@ -918,7 +918,7 @@ TEST(17_AntiParallelDiodes)
|
|||
d1->connect_terminal (db::DeviceClassDiode::terminal_id_C, n2);
|
||||
d2->connect_terminal (db::DeviceClassDiode::terminal_id_A, n2);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' d1 (A=n1,C=n2) (A=1);\n"
|
||||
" device '' d2 (A=n2,C=n1) (A=3);\n"
|
||||
|
|
@ -930,7 +930,7 @@ TEST(17_AntiParallelDiodes)
|
|||
|
||||
// anti-parallel diodes are not combined
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2);\n"
|
||||
" device '' d1 (A=n1,C=n2) (A=1);\n"
|
||||
" device '' d2 (A=n2,C=n1) (A=3);\n"
|
||||
|
|
@ -988,7 +988,7 @@ TEST(20_ParallelMOS3Transistors)
|
|||
d1->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3);
|
||||
d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -998,7 +998,7 @@ TEST(20_ParallelMOS3Transistors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n"
|
||||
"end;\n"
|
||||
|
|
@ -1055,7 +1055,7 @@ TEST(21_AntiParallelMOS3Transistors)
|
|||
d1->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3);
|
||||
d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n2,G=n3,D=n1) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1065,7 +1065,7 @@ TEST(21_AntiParallelMOS3Transistors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n"
|
||||
"end;\n"
|
||||
|
|
@ -1127,7 +1127,7 @@ TEST(22_ParallelMOS3TransistorsDisconnectedGates)
|
|||
circuit->connect_pin (pin_c2.id (), n4);
|
||||
d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n4);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C1=n3,C2=n4);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n4,D=n2) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1139,7 +1139,7 @@ TEST(22_ParallelMOS3TransistorsDisconnectedGates)
|
|||
|
||||
// because of the disconnected gates, devices will no be joined:
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C1=n3,C2=n4);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n4,D=n2) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1197,7 +1197,7 @@ TEST(23_ParallelMOS3TransistorsDifferentLength)
|
|||
d1->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3);
|
||||
d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1209,7 +1209,7 @@ TEST(23_ParallelMOS3TransistorsDifferentLength)
|
|||
|
||||
// because of different length, the devices will not be combined:
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1274,7 +1274,7 @@ TEST(30_ParallelMOS4Transistors)
|
|||
d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1284,7 +1284,7 @@ TEST(30_ParallelMOS4Transistors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n"
|
||||
"end;\n"
|
||||
|
|
@ -1348,7 +1348,7 @@ TEST(31_AntiParallelMOS4Transistors)
|
|||
d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n2,G=n3,D=n1,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1358,7 +1358,7 @@ TEST(31_AntiParallelMOS4Transistors)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n"
|
||||
"end;\n"
|
||||
|
|
@ -1427,7 +1427,7 @@ TEST(32_ParallelMOS4TransistorsDisconnectedGates)
|
|||
d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C1=n3a,C2=n3b,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3a,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3b,D=n2,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1439,7 +1439,7 @@ TEST(32_ParallelMOS4TransistorsDisconnectedGates)
|
|||
|
||||
// not combined because gate is different:
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C1=n3a,C2=n3b,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3a,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3b,D=n2,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1509,7 +1509,7 @@ TEST(33_ParallelMOS4TransistorsDisconnectedBulk)
|
|||
circuit->connect_pin (pin_d2.id (), n0b);
|
||||
d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0b);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D1=n0a,D2=n0b);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0a) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2,B=n0b) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1521,7 +1521,7 @@ TEST(33_ParallelMOS4TransistorsDisconnectedBulk)
|
|||
nl.combine_devices ();
|
||||
nl.purge ();
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D1=n0a,D2=n0b);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0a) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2,B=n0b) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1586,7 +1586,7 @@ TEST(34_ParallelMOS4TransistorsDifferentLength)
|
|||
d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0);
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2,B=n0) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
@ -1598,7 +1598,7 @@ TEST(34_ParallelMOS4TransistorsDifferentLength)
|
|||
|
||||
// not combined because length is different:
|
||||
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit '' (A=n1,B=n2,C=n3,D=n0);\n"
|
||||
" device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n"
|
||||
" device '' d2 (S=n1,G=n3,D=n2,B=n0) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n"
|
||||
|
|
|
|||
|
|
@ -280,7 +280,7 @@ TEST(1_DeviceAndNetExtraction)
|
|||
dump_nets_to_layout (nl, cl, ly, dump_map, cm);
|
||||
|
||||
// compare netlist as string
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit RINGO ();\n"
|
||||
" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
|
||||
" subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n"
|
||||
|
|
@ -312,8 +312,8 @@ TEST(1_DeviceAndNetExtraction)
|
|||
for (db::Netlist::device_class_iterator i = nl.begin_device_classes (); i != nl.end_device_classes (); ++i) {
|
||||
nldup.add_device_class (i->clone ());
|
||||
}
|
||||
nldup.from_string (nl.to_parsable_string ());
|
||||
EXPECT_EQ (nldup.to_parsable_string (), nl.to_parsable_string ());
|
||||
nldup.from_string (nl.to_string ());
|
||||
EXPECT_EQ (nldup.to_string (), nl.to_string ());
|
||||
|
||||
// doesn't do anything here, but we test that this does not destroy anything:
|
||||
nl.combine_devices ();
|
||||
|
|
@ -323,7 +323,7 @@ TEST(1_DeviceAndNetExtraction)
|
|||
nl.purge ();
|
||||
|
||||
// compare netlist as string
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n"
|
||||
" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
|
||||
" subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD);\n"
|
||||
|
|
@ -508,7 +508,7 @@ TEST(2_DeviceAndNetExtractionFlat)
|
|||
// compare netlist as string
|
||||
// NOTE: some of the nets are called IN,OUT but are different ones. They
|
||||
// happen to be the same because they share the same label.
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit RINGO ();\n"
|
||||
" device PMOS $1 (S=$16,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device PMOS $2 (S=VDD,G=$16,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
|
||||
|
|
@ -742,7 +742,7 @@ TEST(3_DeviceAndNetExtractionWithImplicitConnections)
|
|||
dump_nets_to_layout (nl, cl, ly, dump_map, cm);
|
||||
|
||||
// compare netlist as string
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit RINGO ();\n"
|
||||
" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD');\n"
|
||||
" subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD');\n"
|
||||
|
|
@ -777,7 +777,7 @@ TEST(3_DeviceAndNetExtractionWithImplicitConnections)
|
|||
nl.purge ();
|
||||
|
||||
// compare netlist as string
|
||||
EXPECT_EQ (nl.to_parsable_string (),
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit RINGO (FB=FB,OSC=OSC,NEXT=NEXT,'VSSZ,VSS'='VSSZ,VSS','VDDZ,VDD'='VDDZ,VDD');\n"
|
||||
" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD');\n"
|
||||
" subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD');\n"
|
||||
|
|
|
|||
|
|
@ -612,7 +612,7 @@ TEST(4_NetlistSubcircuits)
|
|||
"D:B,+c2p2\n"
|
||||
);
|
||||
|
||||
EXPECT_EQ (nl->to_parsable_string (),
|
||||
EXPECT_EQ (nl->to_string (),
|
||||
"circuit c1 (c1p1=n1a,c1p2=n1c);\n"
|
||||
" subcircuit c2 sc1 (c2p1=n1a,c2p2=n1b);\n"
|
||||
" subcircuit c2 sc2 (c2p1=n1b,c2p2=n1c);\n"
|
||||
|
|
@ -622,9 +622,9 @@ TEST(4_NetlistSubcircuits)
|
|||
"end;\n"
|
||||
);
|
||||
|
||||
nldup->from_string (nl->to_parsable_string ());
|
||||
nldup->from_string (nl->to_string ());
|
||||
|
||||
EXPECT_EQ (nldup->to_parsable_string (),
|
||||
EXPECT_EQ (nldup->to_string (),
|
||||
"circuit c1 (c1p1=n1a,c1p2=n1c);\n"
|
||||
" subcircuit c2 sc1 (c2p1=n1a,c2p2=n1b);\n"
|
||||
" subcircuit c2 sc2 (c2p1=n1b,c2p2=n1c);\n"
|
||||
|
|
|
|||
|
|
@ -97,23 +97,26 @@ class DBLayoutToNetlist_TestClass < TestBase
|
|||
l2n.extract_netlist
|
||||
|
||||
assert_equal(l2n.netlist.to_s, <<END)
|
||||
Circuit TRANS ($1=$1,$2=$2):
|
||||
Circuit INV2 (OUT=OUT,$2=$2,$3=$3,$4=$4):
|
||||
XTRANS $1 ($1=$4,$2=OUT)
|
||||
XTRANS $2 ($1=$3,$2=OUT)
|
||||
XTRANS $3 ($1=$2,$2=$4)
|
||||
XTRANS $4 ($1=$2,$2=$3)
|
||||
Circuit RINGO ():
|
||||
XINV2 $1 (OUT=OSC,$2=FB,$3=VSS,$4=VDD)
|
||||
XINV2 $2 (OUT=$I29,$2=$I20,$3=VSS,$4=VDD)
|
||||
XINV2 $3 (OUT=$I28,$2=$I19,$3=VSS,$4=VDD)
|
||||
XINV2 $4 (OUT=$I30,$2=$I21,$3=VSS,$4=VDD)
|
||||
XINV2 $5 (OUT=$I31,$2=$I22,$3=VSS,$4=VDD)
|
||||
XINV2 $6 (OUT=$I32,$2=$I23,$3=VSS,$4=VDD)
|
||||
XINV2 $7 (OUT=$I33,$2=$I24,$3=VSS,$4=VDD)
|
||||
XINV2 $8 (OUT=$I34,$2=$I25,$3=VSS,$4=VDD)
|
||||
XINV2 $9 (OUT=$I35,$2=$I26,$3=VSS,$4=VDD)
|
||||
XINV2 $10 (OUT=$I36,$2=$I27,$3=VSS,$4=VDD)
|
||||
circuit TRANS ($1=$1,$2=$2);
|
||||
end;
|
||||
circuit INV2 (OUT=OUT,$2=$2,$3=$3,$4=$4);
|
||||
subcircuit TRANS $1 ($1=$4,$2=OUT);
|
||||
subcircuit TRANS $2 ($1=$3,$2=OUT);
|
||||
subcircuit TRANS $3 ($1=$2,$2=$4);
|
||||
subcircuit TRANS $4 ($1=$2,$2=$3);
|
||||
end;
|
||||
circuit RINGO ();
|
||||
subcircuit INV2 $1 (OUT=OSC,$2=FB,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $2 (OUT=$I29,$2=$I20,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $3 (OUT=$I28,$2=$I19,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $4 (OUT=$I30,$2=$I21,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $5 (OUT=$I31,$2=$I22,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $6 (OUT=$I32,$2=$I23,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $7 (OUT=$I33,$2=$I24,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $8 (OUT=$I34,$2=$I25,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $9 (OUT=$I35,$2=$I26,$3=VSS,$4=VDD);
|
||||
subcircuit INV2 $10 (OUT=$I36,$2=$I27,$3=VSS,$4=VDD);
|
||||
end;
|
||||
END
|
||||
|
||||
assert_equal(l2n.probe_net(rmetal2, RBA::DPoint::new(0.0, 1.8)).inspect, "RINGO:FB")
|
||||
|
|
@ -180,23 +183,26 @@ END
|
|||
l2n.extract_netlist
|
||||
|
||||
assert_equal(l2n.netlist.to_s, <<END)
|
||||
Circuit TRANS ($1=$1,$2=$2,$3=$3):
|
||||
Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):
|
||||
XTRANS $1 ($1=$2,$2=$4,$3=IN)
|
||||
XTRANS $2 ($1=$2,$2=$5,$3=IN)
|
||||
XTRANS $3 ($1=$5,$2=OUT,$3=$2)
|
||||
XTRANS $4 ($1=$4,$2=OUT,$3=$2)
|
||||
Circuit RINGO ():
|
||||
XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)
|
||||
XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD)
|
||||
XINV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD)
|
||||
XINV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD)
|
||||
XINV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD)
|
||||
XINV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD)
|
||||
XINV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD)
|
||||
XINV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD)
|
||||
XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)
|
||||
XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)
|
||||
circuit TRANS ($1=$1,$2=$2,$3=$3);
|
||||
end;
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
|
||||
subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);
|
||||
subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);
|
||||
subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);
|
||||
subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);
|
||||
end;
|
||||
circuit RINGO ();
|
||||
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
@ -267,27 +273,30 @@ END
|
|||
l2n.extract_netlist
|
||||
|
||||
assert_equal(l2n.netlist.to_s, <<END)
|
||||
Circuit RINGO ():
|
||||
XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)
|
||||
XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD)
|
||||
XINV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD)
|
||||
XINV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD)
|
||||
XINV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD)
|
||||
XINV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD)
|
||||
XINV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD)
|
||||
XINV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD)
|
||||
XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)
|
||||
XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)
|
||||
Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):
|
||||
DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
|
||||
DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
|
||||
DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
|
||||
DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
|
||||
XTRANS $1 ($1=$2,$2=$4,$3=IN)
|
||||
XTRANS $2 ($1=$2,$2=$5,$3=IN)
|
||||
XTRANS $3 ($1=$5,$2=OUT,$3=$2)
|
||||
XTRANS $4 ($1=$4,$2=OUT,$3=$2)
|
||||
Circuit TRANS ($1=$1,$2=$2,$3=$3):
|
||||
circuit RINGO ();
|
||||
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
|
||||
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
|
||||
end;
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
|
||||
device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
|
||||
device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
|
||||
device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
|
||||
device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
|
||||
subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);
|
||||
subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);
|
||||
subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);
|
||||
subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);
|
||||
end;
|
||||
circuit TRANS ($1=$1,$2=$2,$3=$3);
|
||||
end;
|
||||
END
|
||||
|
||||
# cleanup now
|
||||
|
|
@ -380,25 +389,29 @@ END
|
|||
l2n.extract_netlist
|
||||
|
||||
assert_equal(l2n.netlist.to_s, <<END)
|
||||
Circuit RINGO ():
|
||||
XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)
|
||||
XINV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)
|
||||
XINV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)
|
||||
XINV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)
|
||||
XINV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)
|
||||
Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
|
||||
XINV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
|
||||
XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
|
||||
Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
|
||||
DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
|
||||
DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
|
||||
DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
|
||||
DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
|
||||
XTRANS $1 ($1=$3,$2=VSS,$3=IN)
|
||||
XTRANS $2 ($1=$3,$2=VDD,$3=IN)
|
||||
XTRANS $3 ($1=VDD,$2=OUT,$3=$3)
|
||||
XTRANS $4 ($1=VSS,$2=OUT,$3=$3)
|
||||
Circuit TRANS ($1=$1,$2=$2,$3=$3):
|
||||
circuit RINGO ();
|
||||
subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);
|
||||
subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);
|
||||
subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD);
|
||||
subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD);
|
||||
subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD);
|
||||
end;
|
||||
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
|
||||
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
|
||||
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
|
||||
end;
|
||||
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
|
||||
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
|
||||
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
|
||||
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
|
||||
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
|
||||
subcircuit TRANS $1 ($1=$3,$2=VSS,$3=IN);
|
||||
subcircuit TRANS $2 ($1=$3,$2=VDD,$3=IN);
|
||||
subcircuit TRANS $3 ($1=VDD,$2=OUT,$3=$3);
|
||||
subcircuit TRANS $4 ($1=VSS,$2=OUT,$3=$3);
|
||||
end;
|
||||
circuit TRANS ($1=$1,$2=$2,$3=$3);
|
||||
end;
|
||||
END
|
||||
|
||||
l2n.netlist.combine_devices
|
||||
|
|
@ -406,20 +419,23 @@ END
|
|||
l2n.netlist.purge
|
||||
|
||||
assert_equal(l2n.netlist.to_s, <<END)
|
||||
Circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS'):
|
||||
XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)
|
||||
XINV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)
|
||||
XINV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)
|
||||
XINV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)
|
||||
XINV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)
|
||||
Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
|
||||
XINV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
|
||||
XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
|
||||
Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
|
||||
DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
|
||||
DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
|
||||
DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
|
||||
DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
|
||||
circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');
|
||||
subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);
|
||||
subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);
|
||||
subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD);
|
||||
subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD);
|
||||
subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD);
|
||||
end;
|
||||
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
|
||||
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
|
||||
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
|
||||
end;
|
||||
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
|
||||
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
|
||||
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
|
||||
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
|
||||
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
|
||||
end;
|
||||
END
|
||||
|
||||
# cleanup now
|
||||
|
|
|
|||
|
|
@ -610,8 +610,9 @@ class DBNetlist_TestClass < TestBase
|
|||
assert_equal(d1.parameter(1), 42)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit C ():
|
||||
DDC $1 () [U=-0.5,V=42]
|
||||
circuit C ();
|
||||
device DC $1 () (U=-0.5,V=42);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
|
|||
|
|
@ -56,17 +56,19 @@ class DBNetlistDeviceClasses_TestClass < TestBase
|
|||
circuit.connect_pin(pin_b, n3)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n3):
|
||||
D r1 (A=n1,B=n2) [R=1]
|
||||
D r2 (A=n2,B=n3) [R=3]
|
||||
circuit '' (A=n1,B=n3);
|
||||
device '' r1 (A=n1,B=n2) (R=1);
|
||||
device '' r2 (A=n2,B=n3) (R=3);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n3):
|
||||
D r1 (A=n1,B=n3) [R=4]
|
||||
circuit '' (A=n1,B=n3);
|
||||
device '' r1 (A=n1,B=n3) (R=4);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
@ -102,17 +104,19 @@ END
|
|||
circuit.connect_pin(pin_b, n3)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n3):
|
||||
D c1 (A=n1,B=n2) [C=2]
|
||||
D c2 (A=n2,B=n3) [C=3]
|
||||
circuit '' (A=n1,B=n3);
|
||||
device '' c1 (A=n1,B=n2) (C=2);
|
||||
device '' c2 (A=n2,B=n3) (C=3);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n3):
|
||||
D c1 (A=n1,B=n3) [C=1.2]
|
||||
circuit '' (A=n1,B=n3);
|
||||
device '' c1 (A=n1,B=n3) (C=1.2);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
@ -148,17 +152,19 @@ END
|
|||
circuit.connect_pin(pin_b, n3)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n3):
|
||||
D l1 (A=n1,B=n2) [L=1]
|
||||
D l2 (A=n2,B=n3) [L=3]
|
||||
circuit '' (A=n1,B=n3);
|
||||
device '' l1 (A=n1,B=n2) (L=1);
|
||||
device '' l2 (A=n2,B=n3) (L=3);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n3):
|
||||
D l1 (A=n1,B=n3) [L=4]
|
||||
circuit '' (A=n1,B=n3);
|
||||
device '' l1 (A=n1,B=n3) (L=4);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
@ -192,17 +198,19 @@ END
|
|||
circuit.connect_pin(pin_b, n2)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n2):
|
||||
D d1 (A=n1,C=n2) [A=1]
|
||||
D d2 (A=n1,C=n2) [A=3]
|
||||
circuit '' (A=n1,B=n2);
|
||||
device '' d1 (A=n1,C=n2) (A=1);
|
||||
device '' d2 (A=n1,C=n2) (A=3);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n2):
|
||||
D d1 (A=n1,C=n2) [A=4]
|
||||
circuit '' (A=n1,B=n2);
|
||||
device '' d1 (A=n1,C=n2) (A=4);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
@ -252,17 +260,19 @@ END
|
|||
d2.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_G, n3)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n2,C=n3):
|
||||
D d1 (S=n1,G=n3,D=n2) [L=1,W=2,AS=3,AD=4,PS=13,PD=14]
|
||||
D d2 (S=n1,G=n3,D=n2) [L=1,W=3,AS=4,AD=5,PS=14,PD=15]
|
||||
circuit '' (A=n1,B=n2,C=n3);
|
||||
device '' d1 (S=n1,G=n3,D=n2) (L=1,W=2,AS=3,AD=4,PS=13,PD=14);
|
||||
device '' d2 (S=n1,G=n3,D=n2) (L=1,W=3,AS=4,AD=5,PS=14,PD=15);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n2,C=n3):
|
||||
D d1 (S=n1,G=n3,D=n2) [L=1,W=5,AS=7,AD=9,PS=27,PD=29]
|
||||
circuit '' (A=n1,B=n2,C=n3);
|
||||
device '' d1 (S=n1,G=n3,D=n2) (L=1,W=5,AS=7,AD=9,PS=27,PD=29);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
@ -318,17 +328,19 @@ END
|
|||
d2.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_B, n4)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n2,C=n3,D=n4):
|
||||
D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=2,AS=3,AD=4,PS=13,PD=14]
|
||||
D d2 (S=n1,G=n3,D=n2,B=n4) [L=1,W=3,AS=4,AD=5,PS=14,PD=15]
|
||||
circuit '' (A=n1,B=n2,C=n3,D=n4);
|
||||
device '' d1 (S=n1,G=n3,D=n2,B=n4) (L=1,W=2,AS=3,AD=4,PS=13,PD=14);
|
||||
device '' d2 (S=n1,G=n3,D=n2,B=n4) (L=1,W=3,AS=4,AD=5,PS=14,PD=15);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
Circuit (A=n1,B=n2,C=n3,D=n4):
|
||||
D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=5,AS=7,AD=9,PS=27,PD=29]
|
||||
circuit '' (A=n1,B=n2,C=n3,D=n4);
|
||||
device '' d1 (S=n1,G=n3,D=n2,B=n4) (L=1,W=5,AS=7,AD=9,PS=27,PD=29);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue