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OpenRAM
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3230 Commits

Author SHA1 Message Date
mrg 0d6d707315 Reset write_size to none when it is the same as data word width 2021-07-09 12:31:35 -07:00
Jesse Cirimelli-Low 1a7adcfdad fix vnb and vpb routing in rba 2021-07-08 18:31:55 -07:00
Hunter Nichols c1efa2de59 Added delay function for cacti, moved cacti related delay functions to hierarchy_spice, and trimmed the functions to remove irrelevant options for OpenRAM. 2021-07-07 13:22:30 -07:00
Jesse Cirimelli-Low b5daa51a6c don't use hard coded purpose numbers 2021-07-01 17:31:01 -07:00
mrg 0464ec3f16 Skip 50 tests 2021-07-01 16:38:39 -07:00
mrg 55f09d00a4 Make replica_column sky130 friendly 2021-07-01 16:15:13 -07:00
mrg 879f945aa7 Add risc5 functional tests 2021-07-01 16:13:14 -07:00
Jesse Cirimelli-Low 8a0e3e5caf Merge remote-tracking branch 'origin/dev' into dev 2021-07-01 15:22:29 -07:00
Jesse Cirimelli-Low e280efda7b don't copy pwell pin onto nwell 2021-07-01 15:19:59 -07:00
mrg 6be24d4c6c Only 25 cycles 2021-07-01 12:50:20 -07:00
mrg 3d2b192682 Add conditional spare row/col to a couple unit tests 2021-07-01 12:49:30 -07:00
mrg 2711093442 Improve signal debug output 2021-07-01 12:47:17 -07:00
mrg bbdc728ac5 Edits to functional simulation. 
Use correct .TRAN with max timestep.
Seed functional sim with a 3 writes to start for more read addresses.
Move formatting code to simulation module to share.
 2021-07-01 09:59:13 -07:00
Hunter Nichols 8c48520de6 Added cacti-like model and adapted several functions from cacti into python. 2021-06-30 15:50:54 -07:00
Jesse Cirimelli-Low 278c40f4b7 Merge remote-tracking branch 'origin/dev' into dev 2021-06-30 05:24:23 -07:00
Jesse Cirimelli-Low c9b3f4772e fix bias correspondence points 2021-06-30 05:21:39 -07:00
mrg 4d49851396 Commit prefixGDS.py utility script 2021-06-29 17:06:43 -07:00
mrg 1ae68637ee Utilize same format for output 2021-06-29 17:04:32 -07:00
mrg 91603e7e01 Fix spare+value notation error 2021-06-29 16:44:52 -07:00
mrg f98368f766 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-29 15:47:59 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
Jesse Cirimelli-Low bcc956ecdc merge dev 2021-06-29 11:42:32 -07:00
Jesse Cirimelli-Low 24e42d7cbe refactor adding bias pins 2021-06-29 11:37:07 -07:00
mrg 833b7b98ab Conditional import of array col/row multiple 2021-06-29 11:27:54 -07:00
mrg 4a9f361ab9 Save raw file by default for Xyce. Change command debug level. 2021-06-29 11:27:33 -07:00
mrg ee1c2054d3 Add formatted debug output 2021-06-29 11:26:49 -07:00
mrg 930cc48e16 Add vdd/gnd for all bitcells 2021-06-29 09:37:30 -07:00
mrg d2a1f6b654 Add num_rows/cols to sim 2021-06-29 09:35:33 -07:00
mrg e223d434aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-29 09:34:13 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Jesse Cirimelli-Low c36f471333 add vnb/vpb lvs correspondence points 2021-06-29 02:31:56 -07:00
Jesse Cirimelli-Low c599d8f62c use special purposes with _get_gds_reader 2021-06-23 13:21:19 -07:00
mrg 958f5e45bb Add extra dnwell spacing for single port 2021-06-23 11:14:58 -07:00
mrg ef733bb7aa Optional save supply pin centers for summer project 2021-06-23 10:03:38 -07:00
mrg 28c99dae4a Fix error with uniquify where root has a null 2021-06-22 16:39:10 -07:00
mrg b14992b213 Fix arg off by one error in uniquifyGDS 2021-06-22 16:18:03 -07:00
mrg 288f6cbb9f Rename prefixGDS to uniquifyGDS 2021-06-22 16:15:56 -07:00
mrg 04382a2271 Change number of arguments check in prefixGDS.py 2021-06-22 16:15:31 -07:00
mrg c69eb47a7a Finalize uniquify option for SRAMs 2021-06-22 16:13:33 -07:00
mrg 8095c72fc8 Debug prefixGDS.py utility script 2021-06-22 15:53:45 -07:00
mrg 8d71a98ce9 Make purposes argument to gdsMill. Create prefixGDS.py script. 2021-06-22 14:40:43 -07:00
Hunter Nichols a0921b4afc Merge branch 'dev' into automated_analytical_model 2021-06-22 01:39:38 -07:00
mrg 6e22771794 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-21 17:37:41 -07:00
mrg 58f8c66020 Fix disconnected spare_wen_0_0 2021-06-21 17:36:20 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 470317eaa4 Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules. 2021-06-21 17:20:25 -07:00
Hunter Nichols b408a871f9 Added direction information functions to 2-port bitcell modules 2021-06-21 17:19:15 -07:00
Jesse Cirimelli-Low 3502bec231 Merge remote-tracking branch 'origin/dev' into dev 2021-06-21 15:27:32 -07:00
mrg bb1ac1a38e Fix incorrect bus indexing of spare_wen. Convert internal signals to not use braces. 2021-06-21 15:23:08 -07:00
Jesse Cirimelli-Low 2760beae34 swap sky130 replica bitcell array power bias routing 2021-06-21 15:22:31 -07:00
mrg f3f19aeeeb Remove print statement 2021-06-21 15:16:36 -07:00
mrg 1ce5823df8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-21 13:14:23 -07:00
mrg d53bc98ff5 Exit with error when spice models not found. Use ngspice if no simulator defined. 2021-06-21 13:14:08 -07:00
mrg af31027504 Fix error in 1 spare column Verilog 2021-06-21 13:13:53 -07:00
Jesse Cirimelli-Low 56dc83de47 fix typo 2021-06-18 18:10:12 -07:00
Jesse Cirimelli-Low 2dbe928c09 fix typo 2021-06-18 18:08:57 -07:00
Jesse Cirimelli-Low 4688988434 only check dimensions on single port 2021-06-18 17:46:39 -07:00
Jesse Cirimelli-Low 0008df0204 catch where strap size is zero 2021-06-18 15:24:24 -07:00
Jesse Cirimelli-Low 2eb98083d0 Merge branch 'dev' into laptop_checkpoint 2021-06-18 14:21:39 -07:00
Jesse Cirimelli-Low 8ceece2af6 check for valid dimensions instead of recalcuating 2021-06-18 14:21:02 -07:00
mrg 693a81fa8d Fix spare_wen IO pin names 2021-06-18 10:44:35 -07:00
mrg 1299989332 Fix single spare_wen naming 2021-06-18 08:43:21 -07:00
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
mrg 81d20ec2aa Add spare cols to behavioral Verilog model 2021-06-18 07:23:41 -07:00
Jesse Cirimelli-Low 7b7c72706a merge in dev 2021-06-17 09:49:32 -07:00
Jesse Cirimelli-Low d9afe89770 remove print statement 2021-06-17 03:23:46 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
Hunter Nichols 131ff8bcef Changed the regression test to only run models for the output being tested. 2021-06-16 23:50:20 -07:00
mrg afe0902547 Enable small short func tests 2021-06-16 19:13:50 -07:00
mrg b7f1c8e8fc Fix name for detecting single port 2021-06-16 19:07:56 -07:00
mrg c7c319c11f Use extra bitcell version tag only for single port in sky130 2021-06-16 19:06:12 -07:00
mrg d119a0e7ff Use sky130 bitcell in simulation for BLs 2021-06-16 18:45:53 -07:00
mrg 1e486cd344 Use local spacing rule 2021-06-16 18:41:39 -07:00
Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130. 2021-06-16 17:04:02 -07:00
Jesse Cirimelli-Low e775f7a355 fixed indent 2021-06-16 12:36:00 -07:00
Jesse Cirimelli-Low 2b9df2ff1f uncomment function sim and datasheet generation 2021-06-16 11:23:27 -07:00
mrg 6ac082ce23 Only replace simulator if it is defined. 2021-06-16 10:44:13 -07:00
mrg 1adada9e27 Merge branch 'dev' into xyce 2021-06-16 09:52:17 -07:00
Jesse Cirimelli-Low 25bc178132 extend input rail 2021-06-14 15:13:17 -07:00
Hunter Nichols 4132decd32 Merge branch 'dev' into automated_analytical_model 2021-06-14 14:45:48 -07:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
Hunter Nichols 4d22201055 Changed name of regression test since we currently only test the delay. 2021-06-14 10:57:20 -07:00
mrg 159d0ed603 Fix s_en spacing problem. 2021-06-13 15:08:05 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
mrg d6a72aed37 Add 2x1 perimter pins to satisfy minimum area rule. 2021-06-13 15:00:46 -07:00
mrg 2e23fffadd Fix comment 2021-06-13 14:18:55 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Jesse Cirimelli-Low bee9b07516 fix decoder routing 2021-06-11 18:19:07 -07:00
Jesse Cirimelli-Low 2e72da0e53 rotate input to rail contacts for drc 2021-06-10 14:01:28 -07:00
Jesse Cirimelli-Low 247a388ab5 Merge branch 'dev' into laptop_checkpoint 2021-06-09 18:25:45 -07:00
Jesse Cirimelli-Low 10f561648f remove hierarchical decoder vertial m1 above pins 2021-06-09 18:24:21 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
Hunter Nichols b6b20c1f43 Removed level 0 debug statements for bitlines naming. 2021-06-09 12:53:31 -07:00
Hunter Nichols f25dcf1b63 Fixed issue with bitline name warning occuring when no issue is present. 2021-06-09 12:52:26 -07:00
Hunter Nichols a73bfe6c2c Added more configs for model and data from scn4m_subm run. 2021-06-09 10:35:58 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00