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Fix error in 1 spare column Verilog

This commit is contained in:
mrg 2021-06-21 13:13:53 -07:00
parent 693a81fa8d
commit af31027504
1 changed files with 1 additions and 1 deletions
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2
compiler/base/verilog.py
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@ -230,7 +230,7 @@ class verilog:
if self.num_spare_cols == 1:
self.vf.write(" if (spare_wen{0}_reg)\n".format(port))
self.vf.write(" mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size + num))
self.vf.write(" mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size))
else:
for num in range(self.num_spare_cols):
self.vf.write(" if (spare_wen{0}_reg[{1}])\n".format(port, num))