mirror of https://github.com/VLSIDA/OpenRAM.git
Add conditional spare row/col to a couple unit tests
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2711093442
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@ -23,7 +23,15 @@ class array_test(openram_test):
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globals.init_openram(config_file)
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debug.info(2, "Testing 8x8 array for 6t_cell")
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a = factory.create(module_type="bitcell_array", cols=8, rows=8)
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if OPTS.tech_name == "sky130":
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num_spare_rows = 1
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num_spare_cols = 1
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else:
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num_spare_rows = 0
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num_spare_cols = 0
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a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
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self.local_check(a)
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globals.end_openram()
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@ -24,6 +24,15 @@ class riscv_func_test(openram_test):
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globals.init_openram(config_file)
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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if OPTS.tech_name == "sky130":
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num_spare_rows = 1
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num_spare_cols = 1
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else:
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num_spare_rows = 0
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num_spare_cols = 0
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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@ -38,7 +47,9 @@ class riscv_func_test(openram_test):
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c = sram_config(word_size=32,
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write_size=8,
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num_words=32,
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num_banks=1)
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num_banks=1,
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num_spare_cols=num_spare_cols,
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num_spare_rows=num_spare_rows)
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c.words_per_row=1
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c.recompute_sizes()
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debug.info(1, "Functional test RISC-V memory"
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@ -48,7 +59,7 @@ class riscv_func_test(openram_test):
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c.num_banks))
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s = factory.create(module_type="sram", sram_config=c)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, corner=corner, cycles=50)
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f = functional(s.s, corner=corner, cycles=25)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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