Add conditional spare row/col to a couple unit tests

This commit is contained in:
mrg 2021-07-01 12:49:30 -07:00
parent 2711093442
commit 3d2b192682
2 changed files with 22 additions and 3 deletions

View File

@ -23,7 +23,15 @@ class array_test(openram_test):
globals.init_openram(config_file)
debug.info(2, "Testing 8x8 array for 6t_cell")
a = factory.create(module_type="bitcell_array", cols=8, rows=8)
if OPTS.tech_name == "sky130":
num_spare_rows = 1
num_spare_cols = 1
else:
num_spare_rows = 0
num_spare_cols = 0
a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
self.local_check(a)
globals.end_openram()

View File

@ -24,6 +24,15 @@ class riscv_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
if OPTS.tech_name == "sky130":
num_spare_rows = 1
num_spare_cols = 1
else:
num_spare_rows = 0
num_spare_cols = 0
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
@ -38,7 +47,9 @@ class riscv_func_test(openram_test):
c = sram_config(word_size=32,
write_size=8,
num_words=32,
num_banks=1)
num_banks=1,
num_spare_cols=num_spare_cols,
num_spare_rows=num_spare_rows)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Functional test RISC-V memory"
@ -48,7 +59,7 @@ class riscv_func_test(openram_test):
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, corner=corner, cycles=50)
f = functional(s.s, corner=corner, cycles=25)
(fail, error) = f.run()
self.assertTrue(fail, error)