mirror of https://github.com/VLSIDA/OpenRAM.git
Removed level 0 debug statements for bitlines naming.
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@ -498,10 +498,6 @@ class simulation():
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else:
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self.br_name = br_name_port
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debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
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debug.info(0, "bl name={}, br name={}".format(self.bl_name, self.br_name))
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debug.info(0, "br_name_port[port_pos]={}".format(br_name_port[port_pos]))
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debug.info(0, "mport ending={}".format(str(port) + "_" + str(column_addr)))
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debug.info(0, "self.bitline_column={}".format(self.bitline_column))
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else:
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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