mirror of https://github.com/VLSIDA/OpenRAM.git
Remove print statement
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1ce5823df8
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@ -48,7 +48,7 @@ class sram_config:
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self.num_words_per_bank = self.num_words / self.num_banks
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self.num_bits_per_bank = self.word_size * self.num_words_per_bank
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# If this was hard coded, don't dynamically compute it!
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if not self.words_per_row:
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# Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry)
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@ -65,11 +65,11 @@ class sram_config:
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self.recompute_sizes()
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# Set word_per_row in OPTS
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# Set word_per_row in OPTS
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OPTS.words_per_row = self.words_per_row
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debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row))
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def recompute_sizes(self):
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"""
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Calculate the auxiliary values assuming fixed number of words per row.
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@ -99,14 +99,13 @@ class sram_config:
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+ " Bank addr size: {}".format(self.bank_addr_size))
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num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
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print(num_ports)
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if num_ports == 1:
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if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0):
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debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1)
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if ((self.num_rows + num_ports) % array_row_multiple != 0):
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debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, array_row_multiple), -1)
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def estimate_words_per_row(self, tentative_num_cols, word_size):
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"""
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This provides a heuristic rounded estimate for the number of words
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