mirror of https://github.com/VLSIDA/OpenRAM.git
Utilize same format for output
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91603e7e01
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1ae68637ee
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@ -145,7 +145,7 @@ class functional(simulation):
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for port in self.write_ports:
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addr = self.gen_addr()
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(word, spare) = self.gen_data()
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combined_word = "{0}+{1}".format(spare, word)
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, spare + word, "1" * self.num_wmasks, port)
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self.stored_words[addr] = word
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@ -168,7 +168,7 @@ class functional(simulation):
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self.add_noop_one_port(port)
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else:
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(addr, word, spare) = self.get_data()
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combined_word = "{0}+{1}".format(spare, word)
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(spare + word, port)
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@ -198,7 +198,7 @@ class functional(simulation):
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self.add_noop_one_port(port)
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else:
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(word, spare) = self.gen_data()
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combined_word = "{0}+{1}".format(spare, word)
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, spare + word, "1" * self.num_wmasks, port)
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self.stored_words[addr] = word
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@ -214,7 +214,7 @@ class functional(simulation):
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(word, spare) = self.gen_data()
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wmask = self.gen_wmask()
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new_word = self.gen_masked_data(old_word, word, wmask)
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combined_word = "{0}+{1}".format(spare, word)
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("partial_write", combined_word, addr, wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, spare + word, wmask, port)
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self.stored_words[addr] = new_word
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@ -223,7 +223,7 @@ class functional(simulation):
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else:
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(addr, word) = random.choice(list(self.stored_words.items()))
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spare = self.stored_spares[addr[:self.addr_spare_index]]
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combined_word = "{0}+{1}".format(spare, word)
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combined_word = self.combine_word(spare, word)
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# The write driver is not sized sufficiently to drive through the two
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# bitcell access transistors to the read port. So, for now, we do not allow
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# a simultaneous write and read to the same address on different ports. This
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@ -297,6 +297,12 @@ class functional(simulation):
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self.read_results.append([sp_read_value, dout_port, eo_period, cycle])
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return (1, "SUCCESS")
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def combine_word(self, spare, word):
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if len(spare) > 0:
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return spare + "+" + word
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return word
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def format_value(self, value):
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""" Format in better readable manner """
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@ -314,14 +320,14 @@ class functional(simulation):
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vals = value[self.num_spare_cols:]
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spare_vals = value[:self.num_spare_cols]
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else:
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vals = values
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vals = value
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spare_vals = ""
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# Insert underscores
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vals = delineate(vals)
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spare_vals = delineate(spare_vals)
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return spare_vals + "+" + vals
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return self.combine_word(spare_vals, vals)
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def check_stim_results(self):
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for i in range(len(self.read_check)):
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