mirror of https://github.com/VLSIDA/OpenRAM.git
Optional save supply pin centers for summer project
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@ -45,7 +45,7 @@ class supply_tree_router(router):
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def route(self, vdd_name="vdd", gnd_name="gnd"):
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"""
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Route the two nets in a single layer.
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Route the two nets in a single layer.
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Setting pin stripe will make a power rail on the left side.
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"""
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debug.info(1, "Running supply router on {0} and {1}...".format(vdd_name, gnd_name))
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@ -102,6 +102,16 @@ class supply_tree_router(router):
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debug.info(1, "Routing {0} with {1} pins.".format(pin_name,
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remaining_components))
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# Save pin center locations
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if False:
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debug.info(2, "Creating location file {0}_{1}.csv".format(self.cell.name, pin_name))
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f = open("{0}_{1}.csv".format(self.cell.name, pin_name), "w")
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pin_size = len(self.pin_groups[pin_name])
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for index1, pg1 in enumerate(self.pin_groups[pin_name]):
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location = list(pg1.grids)[0]
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f.write("{0},{1},{2}\n".format(location.x, location.y, location.z))
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f.close()
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# Create full graph
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debug.info(2, "Creating adjacency matrix")
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pin_size = len(self.pin_groups[pin_name])
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@ -140,8 +150,8 @@ class supply_tree_router(router):
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# if pin_name == "gnd":
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# print("\nSRC {}: ".format(src) + str(self.pin_groups[pin_name][src].grids) + str(self.pin_groups[pin_name][src].blockages))
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# print("DST {}: ".format(dest) + str(self.pin_groups[pin_name][dest].grids) + str(self.pin_groups[pin_name][dest].blockages))
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# self.write_debug_gds("post_{0}_{1}.gds".format(src, dest), False)
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# self.write_debug_gds("post_{0}_{1}.gds".format(src, dest), False)
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#self.write_debug_gds("final.gds", True)
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#return
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@ -153,7 +163,7 @@ class supply_tree_router(router):
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for unblock_routes in [False, True]:
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for detour_scale in [5 * pow(2, x) for x in range(5)]:
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debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale))
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# Clear everything in the routing grid.
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self.rg.reinit()
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