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Fix name for detecting single port

This commit is contained in:
mrg 2021-06-16 19:07:56 -07:00
parent c7c319c11f
commit b7f1c8e8fc
1 changed files with 1 additions and 1 deletions
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2
compiler/characterizer/simulation.py
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@ -577,7 +577,7 @@ class simulation():
Gets the signal name associated with the bitlines in the bank.
"""
# FIXME: change to a solution that does not depend on the technology
if OPTS.tech_name == "sky130" and self.total_ports == 1:
if OPTS.tech_name == "sky130" and len(self.all_ports) == 1:
cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
else:
cell_mod = factory.create(module_type=OPTS.bitcell)