mirror of https://github.com/VLSIDA/OpenRAM.git
Use extra bitcell version tag only for single port in sky130
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@ -577,7 +577,7 @@ class simulation():
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Gets the signal name associated with the bitlines in the bank.
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"""
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# FIXME: change to a solution that does not depend on the technology
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if OPTS.tech_name == 'sky130':
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if OPTS.tech_name == "sky130" and self.total_ports == 1:
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cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
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else:
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cell_mod = factory.create(module_type=OPTS.bitcell)
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