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Merge branch 'dev' into automated_analytical_model

This commit is contained in:
Hunter Nichols 2021-06-22 01:39:38 -07:00
parent 294ccf602e 6e22771794
commit a0921b4afc
1 changed files with 3 additions and 7 deletions
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10
compiler/sram/sram_base.py
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@ -701,13 +701,9 @@ class sram_base(design, verilog, lef):
# inputs, outputs/output/bar
inputs = []
outputs = []
if self.num_spare_cols == 1:
inputs.append("spare_wen{}".format(port))
outputs.append("bank_spare_wen{}".format(port))
else:
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)