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Improve signal debug output

This commit is contained in:
mrg 2021-07-01 12:47:17 -07:00
parent bbdc728ac5
commit 2711093442
2 changed files with 14 additions and 12 deletions
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19
compiler/characterizer/functional.py
View File

@ -81,7 +81,11 @@ class functional(simulation):
self.create_graph()
self.set_internal_spice_names()
self.q_name, self.qbar_name = self.get_bit_name()
debug.info(2, "q name={0}\nqbar name={1}".format(self.q_name, self.qbar_name))
debug.info(2, "q:\t\t{0}".format(self.q_name))
debug.info(2, "qbar:\t{0}".format(self.qbar_name))
debug.info(2, "s_en:\t{0}".format(self.sen_name))
debug.info(2, "bl:\t{0}".format(self.bl_name))
debug.info(2, "br:\t{0}".format(self.br_name))
# Number of checks can be changed
self.num_cycles = cycles
@ -346,8 +350,7 @@ class functional(simulation):
random_value = random.randint(1, self.max_data - 1)
data_bits = binary_repr(random_value, self.word_size)
if self.num_spare_cols>0:
# Don't use 0 or max value
random_value = random.randint(1, self.max_col_data - 1)
random_value = random.randint(0, self.max_col_data)
spare_bits = binary_repr(random_value, self.num_spare_cols)
else:
spare_bits = ""
@ -403,11 +406,11 @@ class functional(simulation):
# Write important signals to stim file
self.sf.write("\n\n* Important signals for debug\n")
self.sf.write("* bl: {0}\n".format(self.bl_name.format(port)))
self.sf.write("* br: {0}\n".format(self.br_name.format(port)))
self.sf.write("* s_en: {0}\n".format(self.sen_name))
self.sf.write("* q: {0}\n".format(self.q_name))
self.sf.write("* qbar: {0}\n".format(self.qbar_name))
self.sf.write("* bl:\t{0}\n".format(self.bl_name.format(port)))
self.sf.write("* br:\t{0}\n".format(self.br_name.format(port)))
self.sf.write("* s_en:\t{0}\n".format(self.sen_name))
self.sf.write("* q:\t{0}\n".format(self.q_name))
self.sf.write("* qbar:\t{0}\n".format(self.qbar_name))
# Write debug comments to stim file
self.sf.write("\n\n* Sequence of operations\n")

7
compiler/characterizer/simulation.py
View File

@ -515,8 +515,6 @@ class simulation():
self.sen_name = sen_with_port
debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
debug.info(2, "s_en name = {}".format(self.sen_name))
column_addr = self.get_column_addr()
bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
port_pos = -1 - len(str(column_addr)) - len(str(port))
@ -537,11 +535,12 @@ class simulation():
'{}{}_{}'.format(self.dout_name, port, self.probe_data))
self.sen_name = self.get_sen_name(self.graph.all_paths)
debug.info(2, "s_en name = {}".format(self.sen_name))
#debug.info(2, "s_en {}".format(self.sen_name))
self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size - 1)
self.br_name = "br{0}_{1}".format(port, OPTS.word_size - 1)
debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name))
# debug.info(2, "bl name={0}".format(self.bl_name))
# debug.info(2, "br name={0}".format(self.br_name))
def get_sen_name(self, paths, assumed_port=None):
"""