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OpenRAM
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491 Commits

Author SHA1 Message Date
mrg 8c72d3f2e7 PEP8 and small fix 2020-11-18 14:01:25 -08:00
mrg 8507881ea8 Merge branch 's8_single_port' into dev 2020-11-18 13:59:43 -08:00
jcirimel 50a0b88ef8 fix typo 2020-11-18 11:02:40 -08:00
jcirimel 520b496611 check for cell prop names list 2020-11-18 10:47:05 -08:00
mrg 305b546ad5 PEP8 cleanup 2020-11-17 16:56:00 -08:00
mrg 02c1fac3b8 Remove partial Verilog output 2020-11-17 16:51:08 -08:00
Hunter Nichols ac425643a0 Merge branch 'dev' into characterizer_bug_fixes 2020-11-17 13:22:56 -08:00
Hunter Nichols eaf285639a Added debug measurements along main delay paths in SRAM. WIP. 2020-11-17 12:43:17 -08:00
mrg baae28194b Add custom cell custom port order code. Update setup/hold to use it. 2020-11-17 11:12:59 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg e4bc2c4914 Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg b4342ac527 More cleanup 2020-11-13 17:29:20 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 198c0faf85 Remove special s8 6t names 2020-11-13 07:45:31 -08:00
mrg 662d4ea724 Merge remote-tracking branch 'private/drclvs' into dev 2020-11-12 16:01:07 -08:00
mrg 9eeab14639 Add comment before pininfo 2020-11-12 14:33:42 -08:00
mrg 190234df58 Add PININFO to outputs too 2020-11-12 12:12:53 -08:00
mrg d4c4658c77 Clean up invalid routing layer error message 2020-11-12 09:43:08 -08:00
mrg d3cb22c8c1 Fix pin vs module names issue #26 2020-11-12 09:33:48 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
Matt Guthaus 844b850b74 Fix typo in 1w_1r bitcell 2020-11-03 17:14:45 -08:00
mrg 1de545fc8e Fix row and col cap custom names by adding default. 2020-11-03 13:32:15 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 1890385be1 Use custom cells when needed. 2020-11-03 11:58:25 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
Tim 'mithro' Ansell 95d77119c7 Add caches to GDS related functions in utils.py 
* Cache the GDS reader.
 * Cache the properties (size / pins / etc) measured from the GDS files.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
mrg f6c5f48b4c Default channel route is true 2020-10-28 10:31:05 -07:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg 5bff641c0a Multiport constants can't be static 2020-10-27 09:28:21 -07:00
mrg 575f504e4b Remove static method call 2020-10-27 09:26:40 -07:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg f23fe07893 Add custom layers without defaults 2020-10-26 16:37:00 -07:00
mrg b45a7902c0 PEP8 cleanup 2020-10-26 13:13:38 -07:00
mrg fcb7f42e48 Remove split_wl 2020-10-12 17:27:20 -07:00
mrg 3c2e8754e0 Search all shapes for boundary rather than specify structure 2020-10-08 14:04:19 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
mrg 27d921d2db Fix run-time bug for duplicate instance check 2020-10-06 16:26:35 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg b81cdab0d6 Use unique instance names for channel routes. 2020-10-01 07:43:06 -07:00
mrg bd125e2ed3 Check for duplicate instance names. 2020-10-01 07:17:16 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 4b5bbe755f PEP8 cleanup. Fix cur_slew bug. 2020-09-29 11:13:58 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 4a987bef9a Merge branch 'wlbuffer' into dev 2020-09-28 15:51:45 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
jcirimel 7f8edf6d7c fix replica bitcell col 2020-09-23 00:36:08 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg 8e91ec1770 Add check_pins function 2020-09-08 13:31:50 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
Hunter Nichols 13b1d4613c Moved spice naming checking code from design to the spice base module 2020-08-31 14:36:13 -07:00
mrg c1c1535210 Merge branch 'wlbuffer' into dev 2020-08-27 15:44:29 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 3a692e2846 Comment updates 2020-08-17 14:35:39 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 9d5d632d1a Pins may be below the channel. 2020-07-16 14:23:48 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg e49236f8fc Default drc and lvs errors is skipped. 2020-07-13 14:08:00 -07:00
mrg 716798baae Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. 2020-07-13 13:01:00 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg 27166c75f0 Don't remove temp files during regular openram runs. 2020-07-03 07:00:56 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg c1fedda575 Modifications for min area metal. 
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
 2020-06-30 15:07:34 -07:00
mrg 8cedeeb3d9 Widen pitch of control bus in bank. 2020-06-30 10:57:41 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
Matt Guthaus e97644c424 Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
mrg 07d0f3af8e Only copy end-cap pins to the bank level 2020-06-29 11:46:59 -07:00
mrg 47f541df0e Fix bugs in channel route. 2020-06-28 16:58:28 -07:00
mrg 709535f90f Fix right perimeter pin coordinate bug 2020-06-28 14:47:17 -07:00
mrg bc3de9db05 Pick correct side of pin in channel route. 2020-06-28 14:28:18 -07:00
mrg 94d7000717 Reduce output clutter from gds write 2020-06-26 12:16:54 -07:00
mrg 567675ab31 PEP8 cleanup 2020-06-26 11:47:12 -07:00
mrg d53abba479 Always route the channel route since it is it's own design. 2020-06-25 17:43:44 -07:00
mrg f11afaa63d Refactor channel route to be a design. 2020-06-25 17:30:03 -07:00
mrg 4bc3df8931 Add get_tx_insts and expand add_enclosure 2020-06-24 11:54:36 -07:00