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802143012240bdc23c90f71a3965982b88bba249
OpenRAM/compiler/base
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mrg 8021430122 Fix pbitcell erros
2020-11-13 15:55:55 -08:00
..
channel_route.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
contact.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
custom_cell_properties.py
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
custom_layer_properties.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
delay_data.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
design.py
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
errors.py
Add exception errors file
2020-04-08 16:55:45 -07:00
geometry.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
graph_util.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
hierarchy_design.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
hierarchy_layout.py
Use custom cells when needed.
2020-11-03 11:58:25 -08:00
hierarchy_spice.py
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
lef.py
Add PDK layer names to tech file
2020-11-09 09:10:43 -08:00
pin_layout.py
Clean up invalid routing layer error message
2020-11-12 09:43:08 -08:00
power_data.py
Move classes to individual file.
2019-07-16 15:18:04 -07:00
route.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
utils.py
Use bitcell_base for all bitcells. Fix missing setup_bitcell call
2020-11-02 17:00:15 -08:00
vector.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
verilog.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
wire_path.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
wire_spice_model.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
wire.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00