mrg 93e94e26ec Get vdd/gnd from properties if it is defined.

2020-11-16 10:14:37 -08:00

..

channel_route.py

Remove EOL whitespace globally

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contact.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

custom_cell_properties.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

custom_layer_properties.py

Remove EOL whitespace globally

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delay_data.py

Remove EOL whitespace globally

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design.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

errors.py

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geometry.py

Remove EOL whitespace globally

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graph_util.py

Remove EOL whitespace globally

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hierarchy_design.py

Get vdd/gnd from properties if it is defined.

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hierarchy_layout.py

Get vdd/gnd from properties if it is defined.

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hierarchy_spice.py

Get vdd/gnd from properties if it is defined.

2020-11-16 10:14:37 -08:00

lef.py

Add PDK layer names to tech file

2020-11-09 09:10:43 -08:00

pin_layout.py

Clean up invalid routing layer error message

2020-11-12 09:43:08 -08:00

power_data.py

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route.py

Remove EOL whitespace globally

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utils.py

Use bitcell_base for all bitcells. Fix missing setup_bitcell call

2020-11-02 17:00:15 -08:00

vector.py

Remove EOL whitespace globally

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verilog.py

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wire_path.py

Remove EOL whitespace globally

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wire_spice_model.py

Remove EOL whitespace globally

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wire.py

Remove EOL whitespace globally

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