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OpenRAM
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491 Commits

Author SHA1 Message Date
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg 2243761500 Must transitively cut blockages until no more. 2021-05-05 13:44:06 -07:00
mrg 98fb34c44c Add conditional power pins to Verilog model. 2021-04-30 14:15:32 -07:00
mrg a111ecb74c Fix extra indent that made openlane fail. 2021-04-22 13:05:51 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 584349c911 Add custom parameter for wordline layer 2021-04-21 11:04:01 -07:00
mrg aa5e1fd168 Merge remote-tracking branch 'olofk/verilog_model_features' into dev 2021-04-15 14:41:56 -07:00
Olof Kindgren 688a1f1e60 Add HOLD_DELAY parameter for dout in verilog model 
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:39:49 +02:00
Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:33:57 +02:00
mrg 41226087ba Use separate mXp pin layer if it exists 2021-04-14 13:55:21 -07:00
mrg 3eed6bb8ff Check for None before checking DRC tool 2021-04-14 11:07:38 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg 0e48e020c1 Use pins in computing bbox offsets 2021-04-13 16:24:28 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
ota2 48bc47c686 Set pin label size to use zoom factor from tech specifications 2021-02-27 18:30:57 -05:00
Bob Vanhoof d14a68847e added cell label checker and cell labels to the freepdk technology 2021-02-09 13:09:26 +01:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus eebc2a93b6 Remove redundant pins when adding each pin 2021-01-25 09:36:27 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg db142bcd5a Rename pins to original names 2021-01-21 15:22:54 -08:00
mrg 88f2198524 Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
mrg 4991693f1a Clean up min area 2021-01-13 12:32:17 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 7eb1e2f2d1 Keep previous pin shapes which were used in router pin connections. 2021-01-06 11:31:16 -08:00
mrg d61fcb3be3 Fix lpp erase bug in removing router annotations 2021-01-06 09:39:01 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 6101195b51 Function to remove layout pins. 2020-12-21 12:44:04 -08:00
mrg 878a9cee8a Add channel routes as flat instances to appease Magic extraction. 2020-12-15 16:01:39 -08:00
mrg fd118c62e5 Default zom is None not negative. 2020-12-15 13:27:36 -08:00
mrg 2954f13294 Update temp file to be relative 2020-12-14 14:18:18 -08:00
mrg 9a3776e758 Use default zoom for text 2020-12-14 14:18:00 -08:00
mrg d542b7dd76 Add separate box for pins if it has its own purpose 2020-12-08 10:31:57 -08:00
mrg a2ebaf9f81 Fix typo 2020-12-08 10:31:39 -08:00
mrg 62bf713913 Only remove files at end of openram 2020-12-01 11:19:37 -08:00
mrg 0ccb3487b6 Set default port map 2020-11-24 13:27:11 -08:00
mrg 4e10f6d8a6 Make cell/bitcell custom cell external accessible. 2020-11-24 12:01:00 -08:00
mrg cdcd115cec Fix typos 2020-11-24 10:35:14 -08:00
jcirimel d2bc7340ed finish col cap start row cap 2020-11-24 03:02:55 -08:00
jcirimel f40e5f6dba start of adding additional granularity to 1port col caps 2020-11-23 06:55:47 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg 95573c858c Can redefine number of ports in custom_cell_properties 2020-11-21 08:05:49 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg fbed738b4a Merge multiple cell_name fix. 2020-11-18 16:27:28 -08:00