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439 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 038acd1568 single port rba lvs progress 2022-03-07 01:20:59 -08:00
mrg 67b51ff7f5 Move vdd pin in freepdk45 sense amp from dout 2022-03-06 12:20:54 -08:00
mrg f7e3672c89 Route horizontal supplies in write driver. 2022-03-01 14:37:51 -08:00
mrg 9b90a44d4a Move output in freepdk45 sense amp down to prevent router conflict with supply 2022-02-25 16:20:47 -08:00
mrg 12a6f1f2ee Add missing well tap 2022-02-25 10:44:40 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg aeb9594877 Do not extract bb (bounding box) layer in SCN4M_SUBM tech file 2022-01-13 14:39:34 -08:00
mrg e90ea4e737 Remove label Q_bar from replica_cell_1rw due to Magic port bug 2022-01-13 14:38:59 -08:00
mrg 47690e0076 Merge branch 'dev' into docker 2021-12-29 14:42:32 -08:00
Jesse Cirimelli-Low 8d9166a01b only rba lvs errors is colend body extraction 2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low 9e85d17fbe merge rbc lvs fixes 2021-12-23 21:21:10 -08:00
Jesse Cirimelli-Low cf8c486cea merge sky130_dummy_array 2021-12-22 16:00:59 -08:00
Jesse Cirimelli-Low de60a1c38a merge in opc fixes 2021-12-22 15:53:36 -08:00
Jesse Cirimelli-Low 468de963f6 remove add_mod in sky130 2021-12-22 15:51:49 -08:00
Jesse Cirimelli-Low c24c37a15a Merge branch 'dev' into lvs 2021-12-22 15:46:09 -08:00
Jesse Cirimelli-Low 8a0450afac adjust replica col wls 2021-12-22 15:46:03 -08:00
mrg e6e9d09369 Remove add_mod from sky130 modules 2021-12-17 10:30:55 -08:00
mrg 02364c6cdf Add klayout option in config. No tool specific LVS libs 2021-12-17 10:29:17 -08:00
mrg d555e67fb1 Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
Jesse Cirimelli-Low 4e5744df50 remove add_mod() 2021-12-15 01:36:56 -08:00
Jesse Cirimelli-Low 99981109e8 Merge branch 'dev' into opc_fix 2021-12-15 01:31:21 -08:00
Jesse Cirimelli-Low ddb76c4aff fix dummy array opc 2021-12-15 01:28:30 -08:00
Jesse Cirimelli-Low 8eb6caa248 fix bitcell array opc errors 2021-12-14 22:15:27 -08:00
mrg d8d8636d0f Comment out calibre in freepdk45 2021-11-22 15:54:22 -08:00
mrg 66c9501621 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg fc0516460d Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg 32c7e90662 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 48e35588f4 Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg bfb33ecbb4 Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 779d6ad2b2 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg 735f9cf450 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg 552811b41b Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 43bbd2e722 Fixed incorrect via2 spacing rule in tech file. 2021-11-22 11:33:27 -08:00
mrg 8f296810be Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg 6ee4697711 Change cell names in lvs file 2021-11-22 11:33:27 -08:00
mrg 5d33db0ee4 Add write driver to well connect list 2021-11-22 11:33:27 -08:00
mrg 5dc885a674 Update nwell spacing to be same potential 2021-11-22 11:33:27 -08:00
mrg 2e846cb22f Fix regexes for cells without well taps 2021-11-22 11:33:27 -08:00
mrg acc9b2d223 Connect pwell and bulk when no tap 2021-11-22 11:33:27 -08:00
mrg 141b42dc0e Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg f764ac446c Use Caravel-like sky130 install path with ngspice models. 2021-11-17 13:19:23 -08:00
mrg 968a233b82 Don't install in share/pdk 2021-11-08 09:31:56 -08:00
mrg c102ed728c Move tests to test Makefile 2021-11-03 11:36:19 -07:00
mrg af67b738af Add ability to run a single unit test in docker 2021-11-03 08:32:29 -07:00
mrg d7a20bc69b Debug initial docker run scripts 2021-11-02 15:07:18 -07:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
mrg f2882782e7 Use calibre by default until klayout LVS is clean. 2021-09-20 11:05:49 -07:00
mrg 10753a0802 Change via2 to 65nm to be compatible with Calibre FreePDK45 deck 2021-09-16 15:42:02 -07:00
mrg 0a91bd01c8 Fix DRC and LVS scripts 2021-09-16 15:37:26 -07:00
mrg 8081bea708 Shrink 70nm contacts to 65nm 2021-09-16 15:28:39 -07:00
mrg c5f372c264 Fix via2 to match incorrect FreePDK45 rules 2021-09-15 11:58:31 -07:00
mrg f3d1c6edc3 klayout DRC/LVS working 2021-09-15 11:33:39 -07:00
mrg 554b3f4ca7 Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols de2dae4030 Changed unit capacitance from CACTI estimation to PTM estimation. 2021-08-25 15:23:12 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
mrg c117238fa7 Initial klayout DRC/LVS options 2021-08-03 14:41:09 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
mrg e391186581 Update klayout tech files 2021-07-28 11:42:56 -07:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols a312639ef8 Added tech params for on-resistance and load capacitances 2021-07-21 11:00:32 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
mrg 9720e5af29 Remove default array row/col multiple 2021-06-29 11:28:19 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 8ee6d3be6c Added more data for regression modules. 2021-06-21 17:21:00 -07:00
Jesse Cirimelli-Low 8346ad736e add dimension contraints to other tech files 2021-06-18 14:36:15 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols 7a60eabdfe Add more freepdk45 data from regression model. 2021-06-09 13:31:38 -07:00
Hunter Nichols a73bfe6c2c Added more configs for model and data from scn4m_subm run. 2021-06-09 10:35:58 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
ota2 15e57d89ca fix end subckt typo 2021-02-27 18:28:07 -05:00
ota2 8403749fec Add Q and Qbar labels 2021-02-27 18:27:08 -05:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 4b1c359089 update copyright year. 2021-01-22 11:24:53 -08:00
Hunter Nichols c8e631108a Updated sim_data for scmos 2021-01-22 00:51:14 -08:00
Hunter Nichols 59200d1048 Added updated data for scmos, removed unused files. 2021-01-13 13:09:21 -08:00
Hunter Nichols ed3d39a1b8 Added updated model data with slews and loads. Changed linear regressions to account for additional models. 2021-01-13 13:04:34 -08:00
Hunter Nichols 32ad436153 Added freepdk45 data for linear regression 2020-12-22 15:19:31 -08:00
Hunter Nichols d6177b34f0 Added data which includes corner as an input feature 2020-12-17 12:59:06 -08:00
Hunter Nichols f1f6a1a520 Removed windows end of line characters. 2020-12-15 12:08:31 -08:00
Hunter Nichols 06232dee8f Added leakage and slew data. Added temporary fix to model output format. 2020-12-14 14:32:10 -08:00
Hunter Nichols 25544c3974 Added similar interface to linear regression as elmore 2020-12-14 13:59:31 -08:00
Hunter Nichols b1a7e0e55b Added power data 2020-12-09 15:21:22 -08:00
Hunter Nichols ce9036af76 Moved model scripts to characterizer dir 2020-12-02 13:25:03 -08:00
Hunter Nichols acf8e46b55 Fixed import of utility scripts for model generation 2020-11-20 13:43:36 -08:00