mirror of https://github.com/VLSIDA/OpenRAM.git
merge sky130_dummy_array
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parent
de60a1c38a
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@ -94,7 +94,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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mod=self.strap3)
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alternate_strap = 1
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self.connect_inst(self.get_strap_pins(row, col, name))
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self.connect_inst(self.get_strap_pins(row, col))
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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else:
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@ -103,11 +103,11 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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def add_pins(self):
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# bitline pins are not added because they are floating
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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for bl in range(self.column_size):
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self.add_pin("dummy_bl_{}".format(bl))
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self.add_pin("dummy_br_{}".format(bl))
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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