luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix regexes for cells without well taps

This commit is contained in:
mrg 2021-09-27 15:21:26 -07:00
parent acc9b2d223
commit 2e846cb22f
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
technology/freepdk45/tech/freepdk45.lylvs
View File

@ -214,7 +214,7 @@ end
#connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK")
for pat in %w(pnand* and?_dec port_address* replica_bitcell_array)
for pat in %w(pinv* pnor* pnand* and?_dec* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end

2
technology/scn4m_subm/tech/scn4m_subm.lylvs
View File

@ -164,7 +164,7 @@ connect_global(pwell, "PWELL")
connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK")
for pat in %w(pnand* and?_dec port_address* replica_bitcell_array)
for pat in %w(pinv* pnor* pnand* and?_dec* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end