mirror of https://github.com/VLSIDA/OpenRAM.git
Replaced cacti tech params with already existing params. Added an existence check in design_rules.
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@ -17,7 +17,6 @@ from wire_spice_model import wire_spice_model
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from power_data import power_data
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import logical_effort
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class spice():
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"""
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This provides a set of useful generic types for hierarchy
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@ -548,15 +547,25 @@ class spice():
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w_folded_tr = width/folds
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num_folded_tr = folds
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# Re-created some logic contact to get minwidth as importing the contact
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# module causes a failure
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if "minwidth_contact" in tech.drc:
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contact_width = tech.drc["minwidth_contact"]
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elif "minwidth_active_contact" in tech.drc:
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contact_width = tech.drc["minwidth_active_contact"]
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else:
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debug.warning("Undefined minwidth_contact in tech.")
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contact_width = 0
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# only for drain
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total_drain_w = (tech.spice["w_poly_contact"] + 2 * tech.drc["active_contact_to_gate"]) +\
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(stack - 1) * tech.spice["spacing_poly_to_poly"]
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total_drain_w = (contact_width + 2 * tech.drc["active_contact_to_gate"]) +\
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(stack - 1) * tech.drc["poly_to_poly"]
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drain_h_for_sidewall = w_folded_tr
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total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1)
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if num_folded_tr > 1:
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total_drain_w += (num_folded_tr - 2) * (tech.spice["w_poly_contact"] + 2 * tech.drc["active_contact_to_gate"]) +\
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(num_folded_tr - 1) * ((stack - 1) * tech.spice["spacing_poly_to_poly"])
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total_drain_w += (num_folded_tr - 2) * (contact_width + 2 * tech.drc["active_contact_to_gate"]) +\
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(num_folded_tr - 1) * ((stack - 1) * tech.drc["poly_to_poly"])
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if num_folded_tr%2 == 0:
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drain_h_for_sidewall = 0
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@ -34,6 +34,12 @@ class design_rules(dict):
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"""
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self.rules[b] = c
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def __contains__(self, b):
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"""
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Allows checking existence of rules
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"""
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return b in self.rules
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def __getitem__(self, b):
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"""
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For backward compatibility with existing rules.
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@ -468,8 +468,6 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology
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spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0
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spice["c_junc"] = 5e-16 #F/um^2
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spice["c_junc_sw"] = 5e-16 #F/um
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spice["w_poly_contact"] = 0.065 # um
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spice["spacing_poly_to_poly"] = 0.14 # um
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spice["wire_c_per_um"] = 0 # Temp value
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###################################################
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@ -415,8 +415,6 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology
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spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0
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spice["c_junc"] = 9.276962e-16 #F/um^2
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spice["c_junc_sw"] = 3.181055e-16 #F/um
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spice["w_poly_contact"] = 2*_lambda_
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spice["spacing_poly_to_poly"] = 3*_lambda_
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spice["wire_c_per_um"] = 0 # Temp value
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###################################################
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