mirror of https://github.com/VLSIDA/OpenRAM.git
Change cell names in lvs file
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@ -118,7 +118,7 @@ ngate = nactive & poly
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nsd = nactive - ngate
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cheat("cell_6t", "dummy_cell_6t", "cell_1rw", "dummy_cell_1rw", "cell_2rw", "dummy_cell_2rw", "dff","wordline_driver_0") {
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cheat("cell_1rw", "dummy_cell_1rw", "cell_2rw", "dummy_cell_2rw", "pbitcell", "dummy_pbitcell", "dff") {
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# PMOS transistor device extraction
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extract_devices(mos4("p"), { "SD" => psd, "G" => pgate, "tS" => psd, "tD" => psd, "tG" => poly, "W" => nwell })
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