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single port rba lvs progress

This commit is contained in:
Jesse Cirimelli-Low 2022-03-07 01:20:59 -08:00
parent 1a0861539a
commit 038acd1568
5 changed files with 61 additions and 13 deletions
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6
technology/sky130/modules/sky130_bitcell_array.py
View File

@ -63,8 +63,10 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
row_layout.append(self.cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
mod=self.cell2)
self.connect_inst(self.get_bitcell_pins(row, col))
if col % 2 == 1:
self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
else:
self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
if col != self.column_size - 1:
if alternate_strap:
if row % 2:

37
technology/sky130/modules/sky130_bitcell_base_array.py
View File

@ -61,7 +61,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
self.width = max([x.rx() for x in self.insts])
self.height = max([x.uy() for x in self.insts])
def get_bitcell_pins(self, row, col):
def get_bitcell_pins(self, row, col, swap = False):
"""
Creates a list of connections in the bitcell,
indexed by column and row, for instance use in bitcell_array
@ -69,6 +69,14 @@ class sky130_bitcell_base_array(bitcell_base_array):
bitcell_pins = []
for port in self.all_ports:
bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
if swap:
swap_pins = []
for pin in bitcell_pins:
if "bl" in pin:
swap_pins.append(pin.replace("bl", "br"))
elif "br" in pin:
swap_pins.append(pin.replace("br", "bl"))
bitcell_pins = swap_pins
bitcell_pins.append("gnd") # gnd
bitcell_pins.append("vdd") # vdd
bitcell_pins.append("vdd") # vpb
@ -104,9 +112,9 @@ class sky130_bitcell_base_array(bitcell_base_array):
for port in self.all_ports:
strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
if row == 0:
strap_pins.extend(["gate_top"])
strap_pins.extend(["top_gate"])
else:
strap_pins.extend(["gate_bottom"])
strap_pins.extend(["bot_gate"])
return strap_pins
def get_row_cap_pins(self, row, col):
@ -152,3 +160,26 @@ class sky130_bitcell_base_array(bitcell_base_array):
except:
pin = inst.get_pin("vnb")
self.add_label("vdd", pin.layer, pin.center())
def add_bitline_pins(self):
bitline_names = self.cell.get_all_bitline_names()
for col in range(self.column_size):
for port in self.all_ports:
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
text = "bl_{0}_{1}".format(port, col)
if "Y" in self.cell_inst[0, col].mirror:
text = text.replace("bl", "br")
self.add_layout_pin(text=text,
layer=bl_pin.layer,
offset=bl_pin.ll().scale(1, 0),
width=bl_pin.width(),
height=self.height)
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
text = "br_{0}_{1}".format(port, col)
if "Y" in self.cell_inst[0, col].mirror:
text = text.replace("br", "bl")
self.add_layout_pin(text=text,
layer=br_pin.layer,
offset=br_pin.ll().scale(1, 0),
width=br_pin.width(),
height=self.height)

22
technology/sky130/modules/sky130_dummy_array.py
View File

@ -72,8 +72,11 @@ class sky130_dummy_array(sky130_bitcell_base_array):
row_layout.append(self.dummy_cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
mod=self.dummy_cell2)
self.connect_inst(self.get_bitcell_pins(row, col))
if col % 2 == 1:
self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
else:
self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
#self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size - 1:
if alternate_strap:
if col % 2:
@ -99,6 +102,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
self.add_inst(name=name,
mod=self.strap3)
alternate_strap = 1
self.connect_inst(self.get_strap_pins(row, col, name))
if alternate_bitcell == 0:
alternate_bitcell = 1
@ -108,11 +112,11 @@ class sky130_dummy_array(sky130_bitcell_base_array):
def add_pins(self):
# bitline pins are not added because they are floating
for wl_name in self.get_wordline_names():
self.add_pin(wl_name, "INPUT")
for bl in range(self.column_size):
self.add_pin("bl_0_{}".format(bl))
self.add_pin("br_0_{}".format(bl))
for wl_name in self.get_wordline_names():
self.add_pin(wl_name, "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
#self.add_pin("vpb", "BIAS")
@ -124,13 +128,19 @@ class sky130_dummy_array(sky130_bitcell_base_array):
for col in range(self.column_size):
for port in self.all_ports:
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
text = "bl_{0}_{1}".format(port, col)
if "Y" in self.cell_inst[0, col].mirror:
text = text.replace("bl", "br")
self.add_layout_pin(text=text,
layer=bl_pin.layer,
offset=bl_pin.ll().scale(1, 0),
width=bl_pin.width(),
height=self.height)
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
self.add_layout_pin(text="br_{0}_{1}".format(port, col),
text = "br_{0}_{1}".format(port, col)
if "Y" in self.cell_inst[0, col].mirror:
text = text.replace("br", "bl")
self.add_layout_pin(text=text,
layer=br_pin.layer,
offset=br_pin.ll().scale(1, 0),
width=br_pin.width(),

5
technology/sky130/modules/sky130_replica_bitcell_array.py
View File

@ -321,15 +321,20 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
if len(self.rbls) > 0:
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
mirror = self.replica_col_insts[0].mirror
for (bl_name, pin_name) in zip(names, pin_names):
pin = inst.get_pin(pin_name)
if 'rbl_bl' in bl_name:
if mirror != "MY":
bl_name = bl_name.replace("rbl_bl","rbl_br")
self.add_layout_pin(text=bl_name,
layer=pin.layer,
offset=pin.ll().scale(1, 0),
width=pin.width(),
height=self.height)
elif 'rbl_br' in bl_name:
if mirror != "MY":
bl_name = bl_name.replace("rbl_br","rbl_bl")
self.add_layout_pin(text=bl_name,
layer=pin.layer,
offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),

4
technology/sky130/modules/sky130_replica_column.py
View File

@ -90,8 +90,8 @@ class sky130_replica_column(sky130_bitcell_base_array):
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
self.add_pin("gate_top", "BIAS")
self.add_pin("gate_bottom", "BIAS")
self.add_pin("top_gate", "INPUT")
self.add_pin("bot_gate", "INPUT")
def add_modules(self):
self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")