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OpenRAM
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merge in opc fixes

This commit is contained in:
Jesse Cirimelli-Low 2021-12-22 15:53:36 -08:00
parent 468de963f6 4e5744df50
commit de60a1c38a
4 changed files with 33 additions and 15 deletions
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13
technology/sky130/modules/sky130_bitcell_array.py
View File

@ -42,6 +42,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
self.strap = factory.create(module_type="internal", version="wlstrap")
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
def create_instances(self):
""" Create the module instances used in this design """
@ -66,10 +67,14 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size - 1:
if alternate_strap:
name="row_{}_col_{}_wlstrap_p".format(row, col)
row_layout.append(self.strap2)
self.add_inst(name=name.format(row, col),
mod=self.strap2)
if row % 2:
row_layout.append(self.strap4)
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
mod=self.strap4)
else:
row_layout.append(self.strap2)
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
mod=self.strap2)
alternate_strap = 0
else:
if row % 2:

26
technology/sky130/modules/sky130_dummy_array.py
View File

@ -48,6 +48,8 @@ class sky130_dummy_array(sky130_bitcell_base_array):
self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
self.strap = factory.create(module_type="internal", version="wlstrap")
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
def create_instances(self):
@ -73,16 +75,24 @@ class sky130_dummy_array(sky130_bitcell_base_array):
self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size - 1:
if alternate_strap:
name = "row_{}_col_{}_wlstrap_p".format(row, col)
row_layout.append(self.strap2)
self.add_inst(name=name,
mod=self.strap2)
if col % 2:
row_layout.append(self.strap4)
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
mod=self.strap4)
else:
row_layout.append(self.strap4)
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
mod=self.strap4)
alternate_strap = 0
else:
name="row_{}_col_{}_wlstrap".format(row, col)
row_layout.append(self.strap)
self.add_inst(name=name,
mod=self.strap)
if col % 2:
row_layout.append(self.strap)
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
mod=self.strap)
else:
row_layout.append(self.strap3)
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
mod=self.strap3)
alternate_strap = 1
self.connect_inst(self.get_strap_pins(row, col, name))
if alternate_bitcell == 0:

2
technology/sky130/modules/sky130_internal.py
View File

@ -22,6 +22,8 @@ class sky130_internal(design.design):
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p"
elif version == "wlstrapa":
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa"
elif version == "wlstrapa_p":
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p"
else:
debug.error("Invalid version", -1)
design.design.__init__(self, name=self.name)

7
technology/sky130/modules/sky130_replica_column.py
View File

@ -100,6 +100,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
self.strap1 = factory.create(module_type="internal", version="wlstrap")
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
self.strap3 = factory.create(module_type="internal", version="wlstrapa_p")
self.colend = factory.create(module_type="col_cap", version="colend")
self.edge_cell = self.colend
@ -132,9 +133,9 @@ class sky130_replica_column(sky130_bitcell_base_array):
row_layout.append(self.replica_cell2)
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2)
self.connect_inst(self.get_bitcell_pins(row, 0))
row_layout.append(self.strap2)
self.add_inst(name=name + "_strap_p", mod=self.strap2)
self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p"))
row_layout.append(self.strap3)
self.add_inst(name=name + "_strap", mod=self.strap3)
self.connect_inst(self.get_strap_pins(row, 0))
alternate_bitcell = 0
elif (row == 0):