Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti.

compiler/base/hierarchy_spice.py

@@ -428,7 +428,7 @@ class spice():
         # Get wire values
         c_wire = self.module_wire_c()
         r_wire = self.module_wire_r()
-        # Calculate tau with provided output load then calc delay
+
         tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_wire/2)
         this_delay = self.horowitz(inrisetime, tf, 0.5, 0.5, True)
         inrisetime = this_delay / (1.0 - 0.5)

compiler/base/timing_graph.py

@@ -115,10 +115,7 @@ class timing_graph():
                 else:
                     debug.error("Undefined model_name for analytical timing: {}".format(params["model_name"]),
                                 return_value=1)
-                #cout+=output_edge_mod.get_cin() # logical effort based CIN
-                #cout+=output_edge_mod.get_input_capacitance() #cacti called from module
-                #func = cacti_params["cin_function"]
-                #cout+=output_edge_mod.func()
+
             # If at the last output, include the final output load
             if i == len(path) - 2:
                 cout += load
@@ -130,10 +127,6 @@ class timing_graph():
             else:
                 debug.error("Undefined model_name for analytical timing: {}".format(params["model_name"]),
                             return_value=1)
-            #delays.append(path_edge_mod.analytical_delay(corner, cur_slew, cout))
-            #delays.append(path_edge_mod.cacti_delay(corner, cur_slew, cout, cacti_params))
-            #delays.append(path_edge_mod.cacti_params["delay_function"](corner, cur_slew, cout, cacti_params))
-            cur_slew = delays[-1].slew
 
         return delays
         

compiler/characterizer/cacti.py

@@ -72,14 +72,14 @@ class cacti(simulation):
         for load,slew in load_slews:
             # Calculate delay based on slew and load
             # Calculations expect Farad, input is Femto-Farad
-            load_farad = load*1e-12
-            load_farad = 0.052275e-12
+            load_farad = load*1e-15
+            #load_farad = 0.052275e-12
             slew = 0
             path_delays = self.graph.get_timing(bl_path, self.corner, slew, load_farad, self.params)
 
             total_delay = self.sum_delays(path_delays)
-            debug.info(0, "total_delay={}".format(total_delay))
-            sys.exit()
+            #debug.info(0, "total_delay={}".format(total_delay))
+            #sys.exit()
             delay_ns = total_delay.delay/1e-9
             slew_ns = total_delay.slew/1e-9
             max_delay = max(max_delay, total_delay.delay)

technology/freepdk45/tech/tech.py

@@ -423,9 +423,9 @@ spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
-spice["nom_threshold"] = 0.4    # Typical Threshold voltage in Volts
-spice["wire_unit_r"] = 0.075     # Unit wire resistance in ohms/square
-spice["wire_unit_c"] = 0.64e-12  # Unit wire capacitance F/um^2
+spice["nom_threshold"] = 0.4     # Typical Threshold voltage in Volts
+spice["wire_unit_r"] = 0.25      # Unit wire resistance in ohms/square
+spice["wire_unit_c"] = 2.3e-16   # Unit wire capacitance F/um^2, calculated from CACTI 45dat
 spice["min_tx_drain_c"] = 0.7    # Minimum transistor drain capacitance in ff
 spice["min_tx_gate_c"] = 0.2     # Minimum transistor gate capacitance in ff
 spice["dff_setup"] = 9        # DFF setup time in ps