mirror of https://github.com/VLSIDA/OpenRAM.git
Fix cheat on wordline driver name.
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bfb33ecbb4
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48e35588f4
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@ -206,13 +206,13 @@ connect(metal10, metal10_pin)
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schematic.simplify
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if $connect_supplies
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connect_implicit("vdd")
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connect_implicit("gnd")
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connect_implicit("*", "vdd")
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connect_implicit("*", "gnd")
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end
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#connect_global(pwell, "PWELL")
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#connect_global(nwell, "NWELL")
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#connect_global(bulk, "BULK")
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connect_global(pwell, "PWELL")
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connect_global(nwell, "NWELL")
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connect_global(bulk, "BULK")
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for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*)
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connect_explicit(pat, [ "NWELL", "vdd" ])
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