mirror of https://github.com/VLSIDA/OpenRAM.git
Added tech params for on-resistance and load capacitances
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@ -457,9 +457,15 @@ parameter["sa_inv_nmos_size"] = 0.27 # micro-meters
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parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance
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# Spice Values uses to calculate analytical delay based on CACTI equations
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# FIXME: temp values used currently. Need to be derived from simulations or the SPICE model
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spice["r_nch_on"] = 0
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spice["r_pch_on"] = 0
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spice["i_on_n"] = 0.0004463 # A/um
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spice["i_on_p"] = 0.0000771 # A/um
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spice["tox"] = 0.00114 # microns
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spice["eps_ox"] = 0.00245e-14 # F/um, calculated from CACTI 45nm data
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spice["cox"] = spice["eps_ox"]/spice["tox"] # F/um^2
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spice["c_g_ideal"] = spice["cox"]*drc["minlength_channel"] # F/um
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spice["c_overlap"] = 0.2*spice["c_g_ideal"] # F/um
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spice["c_fringe"] = 0 # F/um, not defined in this technology
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spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0
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###################################################
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# Technology Tool Preferences
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@ -404,9 +404,15 @@ parameter["sa_inv_nmos_size"] = 9 * _lambda_
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parameter["bitcell_drain_cap"] = 0.2 # In Femto-Farad, approximation of drain capacitance
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# Spice Values uses to calculate analytical delay based on CACTI equations
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# FIXME: temp values used currently. Need to be derived from simulations or the SPICE model
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spice["r_nch_on"] = 0
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spice["r_pch_on"] = 0
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spice["i_on_n"] = 0.00060199 # A/um
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spice["i_on_p"] = 0.000108 # A/um
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spice["tox"] = 0.0076 # microns
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spice["eps_ox"] = 0.00859e-14 # F/um, calculated from CACTI 180nm data
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spice["cox"] = spice["eps_ox"]/spice["tox"] # F/um^2
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spice["c_g_ideal"] = spice["cox"]*drc["minlength_channel"] # F/um
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spice["c_overlap"] = 0.2*spice["c_g_ideal"] # F/um
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spice["c_fringe"] = 0 # F/um, not defined in this technology
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spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0
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###################################################
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# Technology Tool Preferences
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