luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Connect pwell and bulk when no tap

This commit is contained in:
mrg 2021-09-27 12:30:06 -07:00
parent 141b42dc0e
commit acc9b2d223
2 changed files with 8 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
technology/freepdk45/tech/freepdk45.lylvs
View File

@ -214,10 +214,10 @@ end
#connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK")
#for pat in %w(pnand*_0 and2_dec_0 port_address* replica_bitcell_array)
# connect_explicit(pat, [ "NWELL", "vdd" ])
# connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
#end
for pat in %w(pnand* and?_dec port_address* replica_bitcell_array)
connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end
#for pat in %w(XOR* XNOR* TLAT* TINV* TBUF* SDFF* OR* OAI* NOR* NAND* MUX* LOGIC* INV* HA* FILLCELL*
# FA* DLL* DLH* DFF* DFFS* DFFR* DFFRS* CLKGATE* CLKBUF* BUF* AOI* ANTENNA* AND*)

14
technology/scn4m_subm/tech/scn4m_subm.lylvs
View File

@ -164,16 +164,10 @@ connect_global(pwell, "PWELL")
connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK")
#for pat in %w(pnand*_0 and2_dec_0 port_address* replica_bitcell_array)
# connect_explicit(pat, [ "NWELL", "vdd" ])
# connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
#end
#for pat in %w(XOR* XNOR* TLAT* TINV* TBUF* SDFF* OR* OAI* NOR* NAND* MUX* LOGIC* INV* HA* FILLCELL*
# FA* DLL* DLH* DFF* DFFS* DFFR* DFFRS* CLKGATE* CLKBUF* BUF* AOI* ANTENNA* AND*)
# connect_explicit(pat, [ "NWELL", "VDD" ])
# connect_explicit(pat, [ "BULK", "VSS" ])
#end
for pat in %w(pnand* and?_dec port_address* replica_bitcell_array)
connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end
# Actually performs the extraction
netlist # ... not really required