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OpenRAM
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439 Commits

Author SHA1 Message Date
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Hadir Khan 698020301c updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
hadirkhan10 b9fd172e44 corrected the pin mapping 2023-10-31 23:24:21 -07:00
hadirkhan10 de7a248ff0 added the cell property definitions 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a904874978 passing gf180 parameterized gate tests 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low d18a4f8c7c additional tech commits 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a18d62c430 rename gf180 to gf180mcu 2023-10-31 23:24:21 -07:00
mrg 06058e1b87 Initial files for gf180 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low 788d7e5474 fix VPB/VNB pins not being found 2023-10-31 18:07:35 -07:00
Bugra Onal d53353b5be Merge branch 'dev' into char 2023-07-19 12:06:34 -07:00
Bugra Onal eddc9af45b Merge branch 'dev' into char 2023-07-10 13:55:50 -07:00
Sam Crow 539dfc979a conform default behavior for sky130 custom modules to unit test 2023-06-07 17:31:12 -07:00
Bugra Onal abd18ab832 Moved freepdk sense amp dout pin away from gnd pin 2023-05-23 15:08:06 -07:00
Bugra Onal 7ed99278bd Sense amp fixes 2023-04-19 12:42:02 -07:00
Bugra Onal dae275c508 Merge branch 'dev' into char 2023-04-12 12:00:31 -07:00
Bugra Onal 027b93ab83 Added buff to sense_amp in freepdk45 2023-04-12 11:49:55 -07:00
Bugra Onal 0ff1d1a23d Added buff to sense_amp in scmos 2023-04-12 11:49:32 -07:00
Jacob Walker ab955f0da8 removed data files 2023-03-30 11:30:50 -07:00
Jacob Walker a64361b9d1 testing data for rom tests 2023-03-30 11:30:50 -07:00
samuelkcrow 672c585355 fixes to the custom module fix 2023-03-04 19:17:29 -08:00
Sam Crow f1d91efebd fix single port by using existing custom modules 2023-03-03 14:17:57 -08:00
mrg 1db9881ce7 Add sky130 corners to tech file. 2023-03-01 09:26:16 -08:00
Bugra Onal 3496ac8f5a Added buffer to sense_amp output (need to resize) 2023-02-21 13:23:29 -08:00
mrg 5a26be52bd Fix path to tech and spice models. 2023-02-17 17:32:30 -08:00
mrg 1b711ed7d7 Include and use FreePDK45 models with license. 2023-02-17 15:37:53 -08:00
Eren Dogan 3bf6ee1a91 Handle tilde in the tech module of freepdk45 2023-01-31 14:39:44 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Jesse Cirimelli-Low 69c988f853 rewrite wordline strap pin copying to not use exceptions 2022-12-19 17:30:05 -08:00
mrg 18df0f55eb Must over-ride build_graph in dummy bitcell. 2022-12-19 11:52:39 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Eren Dogan e8b78bfd74 Fix paths in .magicrc 2022-10-25 14:36:05 -07:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
Jesse Cirimelli-Low 374562f354 rbc substrate issues 2022-06-16 15:17:07 -07:00
Jesse Cirimelli-Low 98fe4c74a4 colend fixes in progress 2022-06-15 22:34:21 -07:00
mrg bbfccd1e00 Remove netlist bl/br swaps on flipped cells 2022-05-23 17:16:36 -07:00
Jesse Cirimelli-Low 825ada8293 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-05-19 21:51:13 -07:00
Jesse Cirimelli-Low 172d070880 fix bl routing in rba 2022-05-19 21:45:48 -07:00
mrg 25fa0a8de3 Fix missing cell syntax error. 2022-05-19 14:53:17 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 7195d81736 Adjust WL and GND for contacted via2 spacing. 2022-04-19 10:32:37 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 68d0a56423 Fix WL to gnd spacing for grounded wordlines. 2022-04-04 16:02:47 -07:00
mrg 111533f0b0 Move power pins to horizontal or vertical layer in all cells. 2022-03-31 16:36:19 -07:00
mrg 83e5848728 Change FreePDK and SCMOS 2rw cell to share gnd power rail. 2022-03-30 13:48:53 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg b75856fac9 Merge branch 'dev' into sky130_fixes 2022-03-09 11:31:42 -08:00
Jesse Cirimelli-Low 0667a93d53 single port rba passing lvs 2022-03-07 13:45:50 -08:00