mirror of https://github.com/VLSIDA/OpenRAM.git
Move tests to test Makefile
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mrg
parent
6f33e8102f
commit
c102ed728c
47
Makefile
47
Makefile
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@ -145,51 +145,6 @@ macros:
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.PHONY: macros
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TEST_DIR = $(TOP_DIR)/compiler/tests
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TEST_SRCS=$(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py)))
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TEST_DIRS=$(basename $(TEST_SRCS))
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TEST_STAMPS=$(addsuffix .ok,$(TEST_DIRS))
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TEST_BROKEN := \
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sky130_sram_1kbyte_1r1w_8x1024_8 \
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sky130_sram_1kbyte_1rw_32x256_8 \
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sky130_sram_2kbyte_1rw_32x512_8 \
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sky130_sram_4kbyte_1rw_32x1024_8 \
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WORKING_TEST_STAMPS=$(filter-out $(addsuffix .ok, (TEST_BROKEN)), $(TEST_STAMPS))
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$(TEST_DIRS):
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@$(MAKE) --no-print-directory $@.ok
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tests:
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@echo "Running the following tests"
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@for S in $(WORKING_TEST_STAMPS); do echo " - $$S"; done
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$(MAKE) $(WORKING_TEST_STAMPS)
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.PHONY: tests
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%.ok: compiler/tests/%.py
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@mkdir -p $*
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@docker run -v $(TOP_DIR):/openram \
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-v $(SKY130_PDK):$(SKY130_PDK) \
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-e PDK_ROOT=$(PDK_ROOT) \
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-e OPENRAM_HOME=/openram/compiler \
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-e OPENRAM_TECH=/openram/technology \
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-e OPENRAM_TMP=/openram/$* \
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--user $(UID):$(GID) \
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vlsida/openram-ubuntu:latest \
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python3 -u /openram/compiler/tests/$*.py -v -k && touch $@
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.DELETE_ON_ERROR: $(TEST_STAMPS)
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regress:
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@docker run -v $(TOP_DIR):/openram \
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-e OPENRAM_HOME=/openram/compiler \
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-e OPENRAM_TECH=/openram/technology \
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--user $(UID):$(GID) \
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vlsida/openram-ubuntu:latest \
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sh -c "python3 -u /openram/compiler/tests/regress.py"
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.PHONY: regress
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mount:
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@docker run -it -v $(TOP_DIR):/openram \
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-v $(SKY130_PDK):$(SKY130_PDK) \
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@ -201,8 +156,6 @@ mount:
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.PHONY: mount
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clean:
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@rm -rf $(TEST_STAMPS)
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@rm -rf $(TEST_DIRS)
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@rm -f *.zip
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.PHONE: clean
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@ -35,7 +35,7 @@ ${CELL_TESTS} \
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${MODULE_TESTS} \
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${TOP_TESTS} \
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${CHAR_TESTS} \
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${USAGE_TESTS}
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${USAGE_TESTS}
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.PHONY: ${ALL_TESTS}
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@ -64,8 +64,8 @@ usage: ${USAGE_TESTS}
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$(ALL_TESTS):
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python3 $@ -t ${TECH}
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OPENRAM_TECHS = $(subst :, ,$(OPENRAM_TECH))
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TECH_DIR := $(word 1, $(foreach dir,$(OPENRAM_TECHS),$(wildcard $(dir)/$(TECH))))
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CONFIG_DIR = $(OPENRAM_HOME)/model_configs
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@ -75,9 +75,9 @@ CSV_DIR = $(TECH_DIR)/sim_data
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# Creates names of technology specific okay files for the configs
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STAMPS=$(addprefix $(SIM_DIR)/, $(addsuffix .ok, $(notdir $(basename $(MODEL_CONFIGS)))))
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OPTS =
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OPTS =
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# Characterize and perform DRC/LVS
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OPTS += -c
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OPTS += -c
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# Do not characterize or perform DRC/LVS
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OPTS += -n
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# Verbosity
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@ -100,8 +100,7 @@ model: $(STAMPS)
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clean_model:
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rm -f -r $(SIM_DIR)/*.ok
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clean:
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find . -name \*.pyc -exec rm {} \;
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find . -name \*~ -exec rm {} \;
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@ -24,24 +24,24 @@ class openram_test(unittest.TestCase):
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def tearDown(self):
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duration = time.time() - self.start_time
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print('%s: %.3fs' % (self.id(), duration))
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def fail(self, msg):
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import inspect
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s = inspect.stack()
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base_filename = os.path.splitext(os.path.basename(s[2].filename))[0]
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try:
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OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
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except:
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debug.error("$OPENRAM_HOME is not properly defined.", 1)
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import shutil
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zip_file = "{0}/../{1}_{2}".format(OPENRAM_HOME, base_filename, os.getpid())
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debug.info(0, "Archiving failed temp files {0} to {1}".format(OPTS.openram_temp, zip_file))
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shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
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# import shutil
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# zip_file = "{0}/../{1}_{2}".format(OPENRAM_HOME, base_filename, os.getpid())
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# debug.info(0, "Archiving failed temp files {0} to {1}".format(OPTS.openram_temp, zip_file))
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# shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
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super().fail(msg)
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def local_drc_check(self, w):
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self.reset()
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@ -55,7 +55,7 @@ class openram_test(unittest.TestCase):
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self.fail("DRC failed: {}".format(w.name))
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elif not OPTS.keep_temp:
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self.cleanup()
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def local_check(self, a, final_verification=False):
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self.reset()
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@ -128,7 +128,7 @@ class openram_test(unittest.TestCase):
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def cleanup(self):
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""" Reset the duplicate checker and cleanup files. """
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files = glob.glob(OPTS.openram_temp + '*')
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for f in files:
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# Only remove the files
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@ -209,16 +209,10 @@ connect_global(pwell, "PWELL")
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connect_global(nwell, "NWELL")
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connect_global(bulk, "BULK")
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#for pat in %w(pnand*_0 and2_dec_0 port_address* replica_bitcell_array)
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# connect_explicit(pat, [ "NWELL", "vdd" ])
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# connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
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#end
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#for pat in %w(XOR* XNOR* TLAT* TINV* TBUF* SDFF* OR* OAI* NOR* NAND* MUX* LOGIC* INV* HA* FILLCELL*
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# FA* DLL* DLH* DFF* DFFS* DFFR* DFFRS* CLKGATE* CLKBUF* BUF* AOI* ANTENNA* AND*)
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# connect_explicit(pat, [ "NWELL", "VDD" ])
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# connect_explicit(pat, [ "BULK", "VSS" ])
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#end
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for pat in %w(pnand* and2_dec* port_address* replica_bitcell_array)
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connect_explicit(pat, [ "NWELL", "vdd" ])
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connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
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end
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# Actually performs the extraction
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netlist # ... not really required
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@ -457,10 +457,10 @@ parameter["sa_inv_nmos_size"] = 0.27 # micro-meters
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parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance
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# Spice Values uses to calculate analytical delay based on CACTI equations
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spice["i_on_n"] = 0.0004463 # A/um
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spice["i_on_n"] = 0.0004463 # A/um
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spice["i_on_p"] = 0.0000771 # A/um
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spice["tox"] = 0.00114 # microns
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spice["eps_ox"] = 0.00245e-14 # F/um, calculated from CACTI 45nm data
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spice["eps_ox"] = 0.00245e-14 # F/um, calculated from CACTI 45nm data
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spice["cox"] = spice["eps_ox"]/spice["tox"] # F/um^2
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spice["c_g_ideal"] = spice["cox"]*drc["minlength_channel"] # F/um
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spice["c_overlap"] = 0.2*spice["c_g_ideal"] # F/um
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@ -477,8 +477,11 @@ spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa
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# Technology Tool Preferences
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###################################################
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drc_name = "calibre"
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lvs_name = "calibre"
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pex_name = "calibre"
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#drc_name = "calibre"
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#lvs_name = "calibre"
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#pex_name = "calibre"
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drc_name = "klayout"
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lvs_name = "klayout"
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pex_name = "klayout"
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blackbox_bitcell = False
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