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Change via2 to 65nm to be compatible with Calibre FreePDK45 deck

This commit is contained in:
mrg 2021-09-16 15:42:02 -07:00
parent 0a91bd01c8
commit 10753a0802
1 changed files with 2 additions and 1 deletions
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3
technology/freepdk45/tech/freepdk45.lydrc
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@ -199,7 +199,8 @@ metal2_gt1500.edges.with_length(4.um,nil).space(1500.nm,euclidian).output("METAL
[ metal2_gt90, metal2_gt270, metal2_gt500, metal2_gt900, metal2_gt1500 ].each { |l| l.forget }
# via2
via2.edges.without_length(70.nm).output("VIA2.1", "VIA2.1 : Minimum/Maximum width of via2 : 70nm")
# FreePDK Calibre deck incorrectly has this as 65nm so we are going to be compatible.
via2.edges.without_length(65.nm).output("VIA2.1", "VIA2.1 : Minimum/Maximum width of via2 : 65nm")
via2.space(85.nm, euclidian).output("VIA2.2", "VIA2.2 : Minimum spacing of via2 : 85nm")
via2.not(metal2).output("VIA2.3", "VIA2.3 : via2 must be inside metal2")
via2.not(metal3).output("VIA2.4", "VIA2.4 : via2 must be inside metal3")