Fixed incorrect via2 spacing rule in tech file.

2021-11-03 12:05:55 -07:00 · 2021-11-03 12:05:55 -07:00 · 43bbd2e722
parent 8f296810be
commit 43bbd2e722
1 changed files with 1 additions and 1 deletions
--- a/technology/freepdk45/tech/tech.py
+++ b/technology/freepdk45/tech/tech.py
@ -337,7 +337,7 @@ drc.add_enclosure("m2",
 # VIA2-3.2 Minimum spacing of Via[2-3]
 drc.add_layer("via2",
              width=0.065,
-              spacing=0.075)
+              spacing=0.085)

 # METALINT.1 Minimum width of intermediate metal
 # METALINT.2 Minimum spacing of intermediate metal