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OpenRAM
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206 Commits

Author SHA1 Message Date
Matt Guthaus aae8566ff2 Update golden delays. Fix uninitialized boolean. 2019-08-05 15:45:59 -07:00
Hunter Nichols 24b1fa38a0 Added graph fixes to handmade multiport cells. 2019-07-30 20:31:32 -07:00
Hunter Nichols c12dd987dc Fixed pbitcell graph edge formation. 2019-07-30 00:49:43 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 3327fa58c0 Add some signal names to functional test comments 2019-07-26 14:49:53 -07:00
Matt Guthaus 8ebc568e8b Minor cleanup. Skip more tests until analytical fixed. 2019-07-26 08:33:06 -07:00
Matt Guthaus 54b312eaf9 Add return type 2019-07-24 17:00:38 -07:00
Matt Guthaus 2f03c594c5 Remove success initialization 2019-07-24 16:59:19 -07:00
Matt Guthaus fb60b51c72 Add check bits. Clean up logic. Move read/write bit check to next cycle. 2019-07-24 16:57:04 -07:00
Matt Guthaus fe0db68965 Refactor to share get_measurement_variant 2019-07-24 11:29:29 -07:00
Matt Guthaus 9cb96bda7d Mostly formatting. Added write measurements. 2019-07-24 10:57:33 -07:00
Matt Guthaus 3df8abd38c Clean up. Split class into own file. 2019-07-24 08:15:10 -07:00
jsowash 01493aab3e Added wmask valuesto functional test through add_wmask() 2019-07-23 15:58:54 -07:00
Hunter Nichols 9696401f34 Added graph exclusions to replica column to reduce s_en paths. 2019-07-16 23:47:34 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 4f3340e973 Cleaned up graph additions to characterizer. 2019-06-25 16:37:35 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Hunter Nichols 36214792eb Removed some debug measurements that were causing failures. 2019-05-28 17:04:27 -07:00
Hunter Nichols ad229b1504 Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking. 2019-05-28 16:55:09 -07:00
Hunter Nichols e2d1f7ab0a Added smarter name checking for the characterizer. 2019-05-27 13:08:59 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols 412f9bb463 Added additional check to bitline to reduce false positives. 2019-05-17 01:56:22 -07:00
Hunter Nichols 03a762d311 Replaced constant string comparisons with enums 2019-05-16 14:18:33 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols a80698918b Fixed test issues, removed all bitcells not relevant for timing graph. 2019-05-15 17:17:26 -07:00
Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux. 2019-05-14 14:44:49 -07:00
Hunter Nichols b30c20ffb5 Added graph creation to characterizer, re-arranged pin creation. 2019-05-14 01:15:50 -07:00
Hunter Nichols b4cce65889 Added incorrect read checking in characterizer. 2019-05-13 19:38:46 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols 910878ed30 Removed bitline measures until hardcoded signal names are made dynamic 2019-03-07 12:30:27 -08:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 01c8405d12 Fix bitline measurement delays and adjusted default delay chain for column mux srams 2019-02-06 00:46:25 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Hunter Nichols c10c9e4009 Refactored some code and other additional improvements. 2019-01-29 23:02:28 -08:00
Hunter Nichols 242a63accb Fixed issues introduced by pdriver additions in model unit test 2019-01-29 16:43:30 -08:00
Hunter Nichols 272267358f Moved all bitline delay measurements to delay class. Added measurements to check delay model. 2019-01-03 05:51:28 -08:00
Hunter Nichols 66b2fcdc91 Added data parsing to measurement objects and adding power measurements. 2018-12-20 15:54:56 -08:00
Hunter Nichols b10ef3fb7e Replaced delay measure statement with object implementation. 2018-12-19 18:33:06 -08:00
Hunter Nichols 0c3c58011b Fixed delay test values. 2018-12-05 00:13:23 -08:00
Hunter Nichols 5f954689a5 In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Hunter Nichols a55d907d03 High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME 2018-11-19 15:40:26 -08:00
Hunter Nichols d3c47ac976 Made delay measurements less dependent on period. 2018-11-18 23:28:49 -08:00
Hunter Nichols 3716030a23 Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. 2018-11-16 16:57:22 -08:00
Matt Guthaus 7b10e3bfec Convert port index lists to three simple lists. 2018-11-08 12:19:40 -08:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols f30e54f33c Cleaned up indexing in variable that records cycle times. 2018-10-10 00:02:03 -07:00
Hunter Nichols 3ac2d29940 Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 6e0a1b8823 Fixed bugs in power simulations. Made regex raw strings to remove warnings 2018-10-04 14:09:09 -07:00
Hunter Nichols c876bbfe73 Changed characterizer control generation to match recent changes in multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli. 2018-10-04 14:09:09 -07:00
Hunter Nichols 88f2238e03 Multiport variable bug fix and removed unused code. 2018-10-04 14:09:09 -07:00
Hunter Nichols e7f92e67d0 Fixed issues with inst_sram that prevented functional test from running after merge. 2018-10-04 14:09:01 -07:00
Hunter Nichols 6c537c4884 Made stim node names more ngspice friendly for interactive mode. Cleaned up cycle comments. Changed ground names in stim and added related comments. 2018-10-04 14:06:43 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols d2120d6910 Moved pin name creation from stimuli to delay and bug fix in find_feasible_period_one_port 2018-10-04 14:06:34 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols ab7d3510b5 Cleaned up result tables to be indexed by port and measurement name. Lib has not been updated, so it crashes there. 2018-10-04 14:04:08 -07:00
Hunter Nichols 346b188372 Improved on some hard coded values which determine the measurements. 2018-10-04 14:04:08 -07:00
Hunter Nichols cfe15d48a4 Added changes to make changing the names of the measurements simple in delay.py. Results in some hardcoded values which is TODO for a fix. 2018-10-04 14:04:08 -07:00
Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols 5cab786e21 Cleaned up analyze and some of its helper functions to be less cluttered. 2018-09-07 17:50:09 -07:00
Hunter Nichols 83f6434476 Gave find_feasible_period a port input. 2018-09-07 00:53:11 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Hunter Nichols ad235c02c6 Added debug code which skips characterization and goes straight to writing the lib. Fixed some syntax issues in the lib file. 2018-09-05 23:27:13 -07:00
Hunter Nichols 1af5bb3758 Remove code bloat and simplified port logic in some cases. Crashes while writing to lib. 2018-09-01 00:10:40 -07:00
Hunter Nichols 60088c2dfb Added changes to lib to allow the default to run. Will crash with multiport options. 2018-08-31 00:42:56 -07:00
Hunter Nichols 6614c3eb51 Altered min_period algorithm to work for multiport. Works for default config but mostly untested for multiport options. 2018-08-30 22:43:56 -07:00
Hunter Nichols 5989a3c952 Expanded run_delay_stimulas to multiport. Bug Fixes as well. 2018-08-30 17:08:34 -07:00
Hunter Nichols 907b7310ee Actually changed the noops default data in this commit. 2018-08-30 15:16:54 -07:00
Hunter Nichols 53fa6108e1 Changed most noops calls to have default input of all 0's. Changed parse_values to return dict even if some values fail. 2018-08-30 15:11:54 -07:00
Hunter Nichols e32c1fdd23 Changed part (4) of analyze to use the updated measure names. 2018-08-30 01:18:34 -07:00
Hunter Nichols 78be724867 Edited find_feasible period to use dynamic naming on its measured values and edited the algorithm to work with multiport. 2018-08-30 00:11:14 -07:00
Hunter Nichols 02cf51d3be Added generic parsing function to capture multiple values. This commit does not run and it messes up some naming conventions 2018-08-29 22:16:42 -07:00
Hunter Nichols 4b515fe1ac Changed create_test_cycles to have targeted ports for characterization rather than all ports always. 2018-08-29 17:16:11 -07:00
Hunter Nichols 775fe7b57c Fixed measure statement stating times. This commit crashes if there are no readwrite ports. 2018-08-29 15:13:31 -07:00
Hunter Nichols 8fad81ff1e Changed delay measures to add additional measure based on # of ports. Measure times are not correct yet. 2018-08-29 00:43:27 -07:00
Hunter Nichols ffe59bdf51 Edited delay measures to handle multiple readwrite ports. This commit is not well tested. 2018-08-29 00:01:22 -07:00
Hunter Nichols fa8434e5f0 Added debug checks for unsupported port options. 2018-08-28 13:01:35 -07:00
Hunter Nichols bd763fa1e3 Fixed naming issue between sram instance and PWL in stimulus 2018-08-28 12:09:02 -07:00
Hunter Nichols 75da5a994b Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports. 2018-08-28 00:30:15 -07:00
Hunter Nichols ba5988ec7f Added write port structure to create_test_cycles. This commit contains test code. 2018-08-27 20:35:29 -07:00
Hunter Nichols d82d3df4a7 Added read port cycle data generation. This commit contains test code in create_test_cycles 2018-08-27 18:17:02 -07:00
Hunter Nichols a0e06809f9 Comments now display port in stim file. 2018-08-27 16:23:23 -07:00
Hunter Nichols 350823d434 Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization 2018-08-27 15:56:42 -07:00
Hunter Nichols 6dc72f5b1e Added additional control signal to stim file based on # of ports. 2018-08-23 17:46:24 -07:00
Hunter Nichols efcb435fde Changed # of address signals to reflect # of ports in delay 2018-08-23 14:49:56 -07:00
Hunter Nichols 9151858449 Characterizer now recognizesmultiple ports and additional DIN/DOUT signals are added to stim file. 2018-08-22 23:45:43 -07:00
Hunter Nichols 21e85297d3 Merge branch 'dev' into multiport_characterization 2018-08-22 14:50:29 -07:00