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OpenRAM
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3,119 Commits 4 Branches 63 Tags 78 MiB
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2739 Commits

Author SHA1 Message Date
mrg c3472b5bc5 Remove old commented code 2020-12-01 13:27:50 -08:00
mrg a31e0dab02 Remove via-to-via path width hack 2020-12-01 13:27:32 -08:00
mrg a5b5f7c22b Change layer away from wordlines 2020-12-01 11:33:55 -08:00
mrg 62bf713913 Only remove files at end of openram 2020-12-01 11:19:37 -08:00
mrg 3829213afe Use and2_dec instead of buf_dec for better wldriver layout 2020-12-01 11:19:12 -08:00
mrg b621c3bdc0 Allow verbose output from scripts with one -v and not unit test 2020-12-01 11:18:27 -08:00
mrg fb4cf0d4d1 Remove env variable from run_lvs script 2020-12-01 09:52:23 -08:00
mrg e817b02ade Fix syntax error. Enable script echo on -v -v. 2020-11-30 09:38:42 -08:00
Tim 'mithro' Ansell 59c6980052 Rework run_script command. 
* Use Python subprocess module.
 * Echo the command output to the console.
 * Print while things are still running.
 2020-11-29 13:03:58 -08:00
Tim 'mithro' Ansell fa5296e621 Improving magic verification shell scripts. 
* Output header at start of script.
 * Output footer at end.
 * Add a bunch more progress report to magic output.
 * Make script return the same exit code as magic.
 2020-11-29 12:19:19 -08:00
mrg 0ccb3487b6 Set default port map 2020-11-24 13:27:11 -08:00
mrg 4e10f6d8a6 Make cell/bitcell custom cell external accessible. 2020-11-24 12:01:00 -08:00
mrg cdcd115cec Fix typos 2020-11-24 10:35:14 -08:00
jcirimel d2bc7340ed finish col cap start row cap 2020-11-24 03:02:55 -08:00
jcirimel f40e5f6dba start of adding additional granularity to 1port col caps 2020-11-23 06:55:47 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg 6e51c3cda0 PEP8 cleanup bitcell_base 2020-11-22 07:11:08 -08:00
mrg 95573c858c Can redefine number of ports in custom_cell_properties 2020-11-21 08:05:49 -08:00
mrg aa03eec943 Fix syntax error. 2020-11-21 07:16:45 -08:00
mrg 4c75bc003e Fix bounding box of replica array to include wordline grounds. 2020-11-21 07:03:59 -08:00
mrg 718c327527 Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
mrg e134e07522 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-20 16:57:14 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 27a652ac1b Fix bounding box of cap arrays 2020-11-20 16:54:53 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
Hunter Nichols 9fd473ce70 Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
Hunter Nichols b201fa4bca Fixed path measurement in delay 2020-11-19 22:53:38 -08:00
mrg b77f168270 Fix original pin name bug in bitcell too. 2020-11-19 15:12:02 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg fbed738b4a Merge multiple cell_name fix. 2020-11-18 16:27:28 -08:00
mrg 8c72d3f2e7 PEP8 and small fix 2020-11-18 14:01:25 -08:00
mrg 8507881ea8 Merge branch 's8_single_port' into dev 2020-11-18 13:59:43 -08:00
jcirimel 50a0b88ef8 fix typo 2020-11-18 11:02:40 -08:00
jcirimel 520b496611 check for cell prop names list 2020-11-18 10:47:05 -08:00
mrg 6cfa20731c Consistent naming in example configs 2020-11-18 09:59:38 -08:00
mrg 305b546ad5 PEP8 cleanup 2020-11-17 16:56:00 -08:00
mrg 02c1fac3b8 Remove partial Verilog output 2020-11-17 16:51:08 -08:00
Hunter Nichols 7a0f5e15db Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later. 2020-11-17 15:05:07 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
Hunter Nichols df4c2bad1f Disabled debug measures that are WIP. 2020-11-17 13:30:18 -08:00
Hunter Nichols ac425643a0 Merge branch 'dev' into characterizer_bug_fixes 2020-11-17 13:22:56 -08:00
Hunter Nichols eaf285639a Added debug measurements along main delay paths in SRAM. WIP. 2020-11-17 12:43:17 -08:00
mrg baae28194b Add custom cell custom port order code. Update setup/hold to use it. 2020-11-17 11:12:59 -08:00
mrg 80333ffacb Fix setup/hold characterization to use custom cell and pin names/orders. 2020-11-17 09:44:03 -08:00
mrg 902b92223f Small fix for finding pin names in timing graph. 2020-11-16 13:57:31 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg 7512aa6e70 Skip test 50 which is too slow 2020-11-16 08:59:25 -08:00