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OpenRAM
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4010 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low d7c3bbea3e crba passing again norbl/leftrbl 2023-10-28 18:05:07 -07:00
Eren Dogan fe379297be Add timestamps to the log file 2023-10-05 14:55:05 -07:00
Sam Crow a5412902c6 all control logic tests pass now 2023-09-27 16:38:57 -07:00
Sam Crow bf49ea744e force multi-delay chain pinouts to be user configurable 2023-09-27 13:15:45 -07:00
Sam Crow 5b282df667 Revert "add drc style drc(full) to run_drc.sh on Tim Edwards recommondation" 
This reverts commit c4a14b9354.
 2023-09-26 11:37:04 -07:00
Sam Crow c4a14b9354 add drc style drc(full) to run_drc.sh on Tim Edwards recommondation 2023-09-25 14:14:27 -07:00
Jesse Cirimelli-Low 2faa067ea6 add support for col offset to rbc; fix rba mirroring 2023-09-12 12:12:21 -07:00
Jesse Cirimelli-Low 0034798787 both rbl replica array working 2023-09-11 11:23:39 -07:00
Eren Dogan b3e1a163d0 Fix derouting wires in the gridless router 2023-09-09 13:32:16 -07:00
Jesse Cirimelli-Low e553f3db41 fix sram.sp spare_wen 2023-09-07 12:24:39 -07:00
Eren Dogan 995cc4f60f Fix typo 2023-09-06 21:38:19 -07:00
Eren Dogan 3f2d61a0fa Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108) 2023-09-03 18:21:31 -07:00
Jesse Cirimelli-Low eb82053ab8 copy router from dev 2023-09-03 13:16:18 -07:00
Jesse Cirimelli-Low 5605154cc2 merge dev 2023-09-02 12:27:38 -07:00
Eren Dogan abb12bd785 Increase non-preferred direction cost in router 2023-09-02 08:00:58 -07:00
Eren Dogan 775922774a Use bbox trees to iterate over shapes in routing region efficiently 2023-09-01 20:37:07 -07:00
Jesse Cirimelli-Low 066d00f44b increase power ring crba width for drc 2023-09-01 02:02:41 -07:00
Eren Dogan d9004f6de6 Print more info for the routing processes 2023-08-31 19:03:31 -07:00
Eren Dogan 8a60684e51 Increase the routing region inflation to be safer 2023-08-31 18:26:45 -07:00
Eren Dogan a9e63efad7 Increase via cost in router 2023-08-31 18:26:04 -07:00
Jesse Cirimelli-Low c9a848550c Revert "merge dev" 
This reverts commit daec840888, reversing
changes made to 29e80e8f25.
 2023-08-30 22:40:35 -07:00
Jesse Cirimelli-Low daec840888 merge dev 2023-08-30 22:04:42 -07:00
Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
Eren Dogan 56bee27ee3 Don't write/read gds files unnecessarily for router 2023-08-29 21:45:52 -07:00
Jesse Cirimelli-Low 8f2e4c6914 power ring working 2023-08-28 22:15:05 -07:00
Jesse Cirimelli-Low 8794070ebc various refactor changes 2023-08-28 12:31:55 -07:00
Eren Dogan e12ab68362 Simplify closest edge calculation in signal escape router 2023-08-28 10:38:53 -07:00
Eren Dogan fa5de05be3 Merge branch 'dev' into gridless_router 2023-08-27 21:17:58 -07:00
Eren Dogan 53cc99f5c1 Perform signal escape routing in smaller regions 2023-08-27 21:16:34 -07:00
Eren Dogan 9df3c2ac59 Return the path in source-to-target order 2023-08-27 21:15:25 -07:00
Eren Dogan 141a4e3380 Don't scale the routing region if no path is found 2023-08-27 15:42:09 -07:00
Jesse Cirimelli-Low ba51149dce placement working for sp capped rba, need fix rowcap patterns 2023-08-26 18:54:07 -07:00
Jesse Cirimelli-Low 036cc54b99 rba done w/o wordline 2023-08-24 02:55:45 -07:00
Jesse Cirimelli-Low 450f8ab0c3 replica col generating, funny dummy cell placement 2023-08-22 00:45:57 -07:00
Jesse Cirimelli-Low f890160601 add nwell routing in bca 2023-08-21 20:12:36 -07:00
Jesse Cirimelli-Low 5a6c78865d singleport bitcell array laying out 2023-08-21 19:24:06 -07:00
Jesse Cirimelli-Low 9ac894e2ef update bitcell array trimming 2023-08-15 11:30:16 -07:00
Sam Crow bb47452baf reapply commit c8a06a1 patch that was incorrectly reverted 2023-08-15 11:07:04 -07:00
Jesse Cirimelli-Low e4c15d33c4 Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor 2023-08-14 18:53:22 -07:00
Sam Crow cd1b0f973d Revert pin/net spice object work 
This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef
 2023-08-14 18:44:51 -07:00
Jesse Cirimelli-Low 0391bf6593 add dummy mirroring for sky130 dp 2023-08-14 14:25:57 -07:00
Jesse Cirimelli-Low 30ee5a0a2e add dummy cell mirroring for sky130 2023-08-14 14:19:58 -07:00
Jesse Cirimelli-Low 74c12f944f mirror skywater dp 2023-08-14 13:59:31 -07:00
Jesse Cirimelli-Low fde1b056dc Merge branch 'dev' into singleport_refactor 2023-08-11 13:45:42 -07:00
Jesse Cirimelli-Low 0111620c91 deepcopy overide for instance 2023-08-11 13:45:24 -07:00
Jesse Cirimelli-Low e23289d5ae merge in dev 2023-08-10 17:04:45 -07:00
Bugra Onal 230454d567 Merge changes from subprocess_fix 2023-08-10 16:21:45 -07:00
Bugra Onal 3f08c848d7 Force to use bash for simulators 2023-08-10 16:05:24 -07:00
Jesse Cirimelli-Low be72bcfa01 trim bitcells and fix replica column excluding 2023-08-10 00:34:16 -07:00
Jesse Cirimelli-Low 3fc2a1e229 remove print statements 2023-08-09 22:59:43 -07:00
Eren Dogan ea02aae40f Find blocked nodes and probes faster 2023-08-09 17:45:49 -07:00
Jesse Cirimelli-Low 6f4ee4ad2d pass modules by pointer not value 2023-08-09 14:06:35 -07:00
Eren Dogan 9ac82060b9 Simplify 'remove' attribute of graph_node 2023-08-08 11:54:12 -07:00
Jesse Cirimelli-Low 1aa04db2b6 add isntance naming templates 2023-08-03 16:24:24 -07:00
Jesse Cirimelli-Low 5e01bad2ee remove whitespace 2023-08-03 00:42:42 -07:00
Eren Dogan fa1b2fc96e Delete unused file 2023-08-02 21:54:45 -07:00
Eren Dogan f8b2c1e9b9 Change OPTS.route_supplies option since there's only one router now 2023-08-02 21:48:29 -07:00
Eren Dogan 8fff4e2635 Organize imports of the new router 2023-08-02 21:35:13 -07:00
Eren Dogan 54fc34392d Remove unnecessary imports 2023-08-02 21:28:21 -07:00
Eren Dogan e1d0902680 Cleanup the new router 2023-08-02 21:26:24 -07:00
Eren Dogan ba8e80d205 Replace layout pins in the new signal escape router 2023-08-02 19:33:48 -07:00
Eren Dogan 87eca6b7db Use the initial bbox to route supply and signals 2023-08-02 18:01:09 -07:00
Eren Dogan 08dad81214 Use the same inflating rules for all shapes in router 2023-08-02 17:48:56 -07:00
Jesse Cirimelli-Low 61cfa55d75 fix replica col 2023-08-02 15:19:48 -07:00
Eren Dogan 5b0f97860a Calculate bbox inside the router 2023-08-02 09:30:50 -07:00
Eren Dogan 937585d23c Route signals to the perimeter in sorted order 2023-08-01 21:17:43 -07:00
Eren Dogan 877f20e071 Use the new routers in ROMs 2023-08-01 19:10:02 -07:00
Jesse Cirimelli-Low 5a764c9d43 remove MY mirroring in scmos 2023-08-01 19:05:55 -07:00
Eren Dogan 887a66553b Implement signal escape router using the new gridless router 2023-08-01 12:46:02 -07:00
Eren Dogan dd152da5c2 Change signal escape router's high-level function name 2023-08-01 11:26:25 -07:00
Eren Dogan 42257fb7f8 Export router_tech again 2023-08-01 11:25:12 -07:00
Eren Dogan 993b47be4c Remove old routers from sram_1bank 2023-08-01 11:22:50 -07:00
Eren Dogan 93a6549539 Fix typo 2023-08-01 11:10:32 -07:00
Eren Dogan 6c70396a05 Remove grid-based routers and replace them with the gridless router 2023-08-01 10:59:55 -07:00
Eren Dogan da24c52c52 Cleanup graph router 2023-07-31 21:49:14 -07:00
Eren Dogan db2a276077 Split graph router class to use it for signal escaping later 2023-07-31 19:43:09 -07:00
Eren Dogan 7be6f2783b Refix logic mistake in graph router 2023-07-31 12:24:31 -07:00
Jesse Cirimelli-Low d9d8cb2983 capped norbl scmos passing 2023-07-30 22:39:23 -07:00
Jesse Cirimelli-Low 6b12d442fa placement fixed 2023-07-30 22:01:30 -07:00
Jesse Cirimelli-Low 811eb43459 working on updated placemet code 2023-07-30 20:06:40 -07:00
Eren Dogan 4b2659a5e2 Fix another logic typo 2023-07-30 18:27:17 -07:00
Eren Dogan 5cf774b53e Remove unnecessary lines 2023-07-30 10:09:13 -07:00
Eren Dogan e5bc7b4e95 Fix logic typo 2023-07-30 10:08:57 -07:00
Eren Dogan d487f788e3 Add constant cost for all non-preferred edges 2023-07-29 21:48:33 -07:00
Eren Dogan 821c763a1e Cleanup graph router 2023-07-29 20:01:58 -07:00
Jesse Cirimelli-Low 4d6e836b20 revert bitcell test numbers 2023-07-29 17:43:09 -07:00
Jesse Cirimelli-Low c1acdadd81 remove print statements 2023-07-29 17:39:27 -07:00
Eren Dogan 3b0997e7cf Implement custom add_route() for the graph router 2023-07-29 08:18:49 -07:00
Eren Dogan 4c73d3aa7c Use safe regions to protect pin nodes 2023-07-29 08:17:00 -07:00
Jesse Cirimelli-Low 6f9618f28a fix 2023-07-28 21:46:07 -07:00
Jesse Cirimelli-Low 8d8f243f99 scmos passing with odd sizses again 2023-07-27 18:39:18 -07:00
Eren Dogan 091d0f8775 Convert pins and blockages for graph router 2023-07-26 21:46:30 -07:00
Eren Dogan 8522e0108c Add center nodes for existing vias 2023-07-26 21:45:35 -07:00
Jesse Cirimelli-Low a6e07aa364 cleanup 2023-07-26 18:53:39 -07:00
Jesse Cirimelli-Low dde4103d49 scmos pass 2023-07-26 18:40:37 -07:00
Jesse Cirimelli-Low 8a4b34dee1 proper tiling 2023-07-26 18:05:36 -07:00
Eren Dogan 4d835e98b7 Simplify merging new shapes in graph router 2023-07-26 16:44:57 -07:00
Eren Dogan 53505e2ed2 Add "pin safe" functionality to is_node_blocked() 2023-07-26 16:41:46 -07:00
Jesse Cirimelli-Low 4baec81f82 lvs failures 2023-07-26 02:51:31 -07:00
Jesse Cirimelli-Low 3fe44a3751 scmos array placing 2023-07-26 01:28:50 -07:00