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OpenRAM
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lvs failures

This commit is contained in:
Jesse Cirimelli-Low 2023-07-26 02:51:31 -07:00
parent 3fe44a3751
commit 4baec81f82
2 changed files with 6 additions and 30 deletions
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27
compiler/modules/bitcell_base_array.py
View File

@ -185,33 +185,6 @@ class bitcell_base_array(design):
dir_x = True
return (tempy, dir_x)
# def place_array(self, name_template: str, row_offset=0):
# # We increase it by a well enclosure so the precharges don't overlap our wells
# self.height = self.row_size * self.cell.height
# self.width = self.column_size * self.cell.width
#
# xoffset = 0.0
# for col in range(self.column_size):
# yoffset = 0.0
# tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
#
# for row in range(self.row_size):
# tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
#
# if dir_x and dir_y:
# dir_key = "XY"
# elif dir_x:
# dir_key = "MX"
# elif dir_y:
# dir_key = "MY"
# else:
# dir_key = ""
#
# self.cell_inst[row, col].place(offset=[tempx, tempy],
# mirror=dir_key)
# yoffset += self.cell.height
# xoffset += self.cell.width
def place_array(self):
self.pattern.place_array()

9
compiler/modules/pattern.py
View File

@ -129,16 +129,19 @@ class pattern():
place_x = 0
place_y = 0
for i in range(self.num_core_y):
x = 0
place_x = 0
for j in range (self.num_core_x):
print("placing {} {}".format(x,y))
self.place_block(self.core_block, x, y, place_x, place_y)
place_x += self.core_block_width
x += len(self.core_block[0])
x = 0
place_x = 0
y += len(self.core_block)
place_y += self.core_block_height
self.parent_design.width = x
self.parent_design.height = y