 mrg
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611a4155b9
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Add initial custom layer properties.
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2020-10-27 15:11:04 -07:00 |
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mrg
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5bff641c0a
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Multiport constants can't be static
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2020-10-27 09:28:21 -07:00 |
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mrg
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575f504e4b
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Remove static method call
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2020-10-27 09:26:40 -07:00 |
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mrg
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07ef43eaf8
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Convert design class data to static
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2020-10-27 09:23:11 -07:00 |
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mrg
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f23fe07893
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Add custom layers without defaults
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2020-10-26 16:37:00 -07:00 |
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mrg
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dc991cbcab
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Use pin of pgate to figure out supply layer.
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2020-10-26 15:54:16 -07:00 |
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mrg
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38ba5fc10d
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Use pin of pgate to figure out supply layer.
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2020-10-26 15:53:22 -07:00 |
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mrg
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b45a7902c0
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PEP8 cleanup
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2020-10-26 13:13:38 -07:00 |
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mrg
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cae41c63f0
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Merge branch 'spmodels' into dev
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2020-10-23 16:23:12 -07:00 |
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mrg
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b4ebbdd5df
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Require either device models or device library. Remove sky130 flag.
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2020-10-23 14:07:26 -07:00 |
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mrg
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f97ae723f0
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Remove extraneous config files.
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2020-10-23 13:56:27 -07:00 |
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mrg
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cbf9c48504
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Names in skiptests changed. Reduce grid router verbosity.
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2020-10-23 09:22:59 -07:00 |
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mrg
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dcd29214bc
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Temp fix to use old device names during Calibre LVS.
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2020-10-21 17:05:48 -07:00 |
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mrg
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3d5c73709b
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Merge branch 'dev' into spmodels
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2020-10-19 14:49:07 -07:00 |
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mrg
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7da3653ce5
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Only output wmask to lib file in w or rw ports.
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2020-10-16 16:59:51 -07:00 |
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mrg
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3295a813d6
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Don't use single slew for nominal corner
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2020-10-16 16:51:28 -07:00 |
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mrg
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35c91168f7
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Add load/slew scale option to config files
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2020-10-16 13:52:36 -07:00 |
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mrg
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804814d18d
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Add bitlines to dummy modules
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2020-10-16 13:43:56 -07:00 |
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mrg
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20be7caf98
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Make conditional wl and bl for dummy rows/cols.
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2020-10-15 13:56:37 -07:00 |
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mrg
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af40f3077c
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Change sky130 device cards to start with X
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2020-10-15 13:56:10 -07:00 |
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mrg
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b4f293b311
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Merge branch 'dev' into spmodels
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2020-10-15 09:46:16 -07:00 |
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mrg
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6a1f12b62d
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Refactored to utilize OOP
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2020-10-13 11:07:31 -07:00 |
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mrg
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68d74737f7
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Different bitcell and array supply pins
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2020-10-13 07:41:21 -07:00 |
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mrg
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555e776712
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Merge branch 'dev' into spmodels
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2020-10-13 06:41:26 -07:00 |
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 jcirimel
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05667d784f
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move sky130 specific stuff to tech module lib
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2020-10-13 04:48:10 -07:00 |
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mrg
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fcb7f42e48
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Remove split_wl
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2020-10-12 17:27:20 -07:00 |
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mrg
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ca2ce8b070
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Default bitcell opt1
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2020-10-12 17:08:32 -07:00 |
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mrg
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6b56c833df
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Merge branch 'dev' into spmodels
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2020-10-12 15:51:40 -07:00 |
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mrg
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ef310970bf
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Use new Google PDK lib
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2020-10-12 15:46:11 -07:00 |
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mrg
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c3d6be27be
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Fix argument name bug for remove wordlines
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2020-10-08 16:58:38 -07:00 |
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mrg
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3648401e67
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Remove another boundary subcell
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2020-10-08 16:58:19 -07:00 |
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mrg
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8d5db50062
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Fix missing update for left RBL offset
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2020-10-08 16:40:53 -07:00 |
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mrg
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b0b15e8151
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Fix indent bug that failed to create rbl wl pin labels.
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2020-10-08 15:28:01 -07:00 |
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mrg
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01fe02bd90
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Fixes to replica bitline array.
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
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2020-10-08 14:53:44 -07:00 |
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mrg
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03e1b9c50d
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Clean up custom cells
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2020-10-08 14:22:09 -07:00 |
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mrg
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8a9bf2d4f0
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Remove hardcoded structure
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2020-10-08 14:07:46 -07:00 |
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mrg
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3c2e8754e0
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Search all shapes for boundary rather than specify structure
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2020-10-08 14:04:19 -07:00 |
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mrg
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43d2058b3c
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Remove temp files
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2020-10-08 10:35:27 -07:00 |
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mrg
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76ab48def5
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Remove temp files
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2020-10-08 10:33:45 -07:00 |
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mrg
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9a0fc8047b
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Remove diff
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2020-10-08 09:53:52 -07:00 |
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mrg
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7076c376e0
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Remove log from branch
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2020-10-08 09:53:17 -07:00 |
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jcirimel
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1e7ae06b7e
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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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2020-10-08 05:32:03 -07:00 |
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jcirimel
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d40c3588ed
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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jcirimel
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4a1a7e637e
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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mrg
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483f6b187c
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RBL driver supply location differs for sky130 and other techs
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2020-10-06 16:47:32 -07:00 |
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mrg
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c2629edc1b
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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mrg
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27d921d2db
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Fix run-time bug for duplicate instance check
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2020-10-06 16:26:35 -07:00 |
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mrg
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ba432669a1
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Add various riscv examples
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2020-10-06 16:25:44 -07:00 |
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jcirimel
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13e2a9f5f7
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fix missed self.left_rbl refactor
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2020-10-06 05:11:15 -07:00 |
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jcirimel
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888646cdf9
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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