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OpenRAM
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629 Commits

Author SHA1 Message Date
Matt Guthaus 3f57853969 Use lower case names except for leaf cells and top level 2018-07-18 15:10:57 -07:00
Matt Guthaus 4a139b682d Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
Matt Guthaus a9c0ec5549 Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
Matt Guthaus a878ce5500 Standardize DRC and LVS message levels 2018-07-18 14:28:43 -07:00
Matt Guthaus 58896a6f8e Fix control signal names on control_logic input 2018-07-18 13:41:44 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus f43d4cc98f Fix routing clk connections of dff arrays 2018-07-18 11:38:58 -07:00
Matt Guthaus 0701fceb0b Use sram rather than new meta-sram class in the characterizer for delay 2018-07-18 10:39:29 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8a3bc9b1a Space hier decoder input connections along rails to avoid conflicts 2018-07-18 10:21:58 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00
Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array 2018-07-17 15:01:31 -07:00
Matt Guthaus 6133d54684 Fix spacing between adjacent decoders 2018-07-17 15:01:16 -07:00
Matt Guthaus ffc866ef78 Single bank working except for channel routing error in 4-way case. 2018-07-17 14:40:04 -07:00
Matt Guthaus 7a69fc1bca Add col addr routing and data routing 2018-07-17 14:24:44 -07:00
Matt Guthaus 0665d51249 Must connect clock at top level for now 2018-07-17 14:24:07 -07:00
Matt Guthaus e82f97cce1 Add create_bus and connect_bus api 2018-07-17 14:23:29 -07:00
Matt Guthaus 0175c88a16 Convert predecodes to use create_bus api 2018-07-17 14:23:06 -07:00
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus 77e786ae5e Fix bug in recomputing boundary with a new offset 2018-07-16 13:46:12 -07:00
Matt Guthaus afcc3563ae Add new supplies to RBL and control logic 2018-07-16 12:58:15 -07:00
Matt Guthaus 93e830e800 Add new supplies to replica bitline 2018-07-16 10:49:43 -07:00
Matt Guthaus 3bbb604504 Add new power supplies to delay chain 2018-07-16 10:19:52 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 834fbac8de Remove extra print statements. 
Add wrappers for file generation in sram wrapper class.
 2018-07-13 09:38:43 -07:00
Matt Guthaus 0c23efe49b Reference local sram instance in sram.py. 2018-07-13 09:30:14 -07:00
Michael Timothy Grimes 2388ddbfb0 deleting code added in error to pbitcell_array_test during previous commit 2018-07-12 23:55:54 -07:00
Michael Timothy Grimes ba43b986ae merging changes with pbitcell_array test 2018-07-12 23:51:44 -07:00
Michael Timothy Grimes a64ca423c6 changing pbitcell_array test to include an important permutation of the design 2018-07-12 23:45:47 -07:00
Michael Timothy Grimes 7b315a3b69 updating inverter to write transistor spacings 2018-07-12 20:52:05 -07:00
Matt Guthaus a4c29ea527 Improve openram output. Fix save output function name. 2018-07-12 10:35:38 -07:00
Matt Guthaus e6b1fcb44c Refactor banks to use inheritance with a top-level SRAM wrapper class. 2018-07-12 10:30:45 -07:00
Matt Guthaus c71ea51e2e Merge branch 'multiport_cleanup' of github.com:VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:41 -07:00
Matt Guthaus 22d40364ec Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:06 -07:00
Matt Guthaus a2d8d16c7a Split DATA into DIN and DOUT in characterizer 2018-07-11 14:19:09 -07:00
Matt Guthaus 33bb98894f Disable LEF test until supplies fixed. 2018-07-11 14:18:53 -07:00
Matt Guthaus 8be88d14a7 Disable banner output during gitlab runner 2018-07-11 14:18:36 -07:00
Matt Guthaus 7d8352a04d Fix order of checkpointing so that it is done after characterizer and verify have found their executables. 2018-07-11 12:12:03 -07:00
Matt Guthaus 8a530da2cc Remove extra conversion to list 2018-07-11 12:07:37 -07:00
Matt Guthaus 265b5d977a Fix option reload problems and checkpointing so that it works properly. 2018-07-11 12:00:15 -07:00
Matt Guthaus 58646ab8e6 Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
Matt Guthaus f894ef47af Fix missing list conversion to run drc library tests. 2018-07-11 11:58:22 -07:00
Matt Guthaus b3732f4fcf Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
Matt Guthaus f82591dd6f Remove outdated README 2018-07-11 09:12:20 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
 2018-07-10 16:39:32 -07:00
Matt Guthaus d95a1925d4 Refactor banked SRAM into multiple files and dynamically load in SRAM 2018-07-10 14:17:09 -07:00
Matt Guthaus 19c53cd50c Do not fail assertion in exception code. 2018-07-10 14:16:18 -07:00
Matt Guthaus 707f303eb7 Fix syntax error in sram.py 2018-07-10 10:34:54 -07:00
Matt Guthaus f5855ee68a Fix analytical power of contact with new hierarchy_design level introduced. 2018-07-10 10:17:23 -07:00
Matt Guthaus 25cf57ede5 Push create bus functions down into layout class. 2018-07-10 10:06:59 -07:00
Matt Guthaus 98f1914e9f Fix width of decoder with new input bus. Bank tests work again. 2018-07-10 09:31:41 -07:00
Matt Guthaus 019512bc25 Fix python3 module reference in functional test 2018-07-09 16:07:53 -07:00
Matt Guthaus f234e43241 Reset new hierarchy_design instead of design for duplicate GDS name checker 2018-07-09 16:07:30 -07:00
Matt Guthaus bbc98097ac Add getpass include to unit test 30 2018-07-09 15:53:37 -07:00
Matt Guthaus 7bf271fd63 Skip pex and functional tests which are not working. 2018-07-09 15:52:07 -07:00
Matt Guthaus 9d5e5086a1 Add new extra design class with additional hierarchy for shared design rules 2018-07-09 15:43:26 -07:00
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00
Matt Guthaus 2e5d60ae87 Fix input height error for input rail pins 2018-07-09 14:45:27 -07:00
Matt Guthaus e60d157310 Add input pin rails to hierarchical decoder for easier connections at SRAM level. 2018-07-09 13:16:38 -07:00
Matt Guthaus 5cf62e82cf Merge branch 'dev' into multiport_cleanup 2018-07-09 09:58:13 -07:00
Matt Guthaus af84742c19 Simplify m2 pitch calculation 2018-07-09 09:57:57 -07:00
Matt Guthaus a9a95ebf7c Fix pex test permissions 2018-07-09 09:11:14 -07:00
Matt Guthaus b3dc6560f5 Remove regress.sh script 2018-07-09 09:10:12 -07:00
Matt Guthaus 5d32a426c4 Change test sram path so jobs can be simultaneously run. 2018-07-06 07:34:38 -07:00
Matt Guthaus 733be110a2 Add negation to return code so tests fail or pass properly. 2018-07-06 07:27:26 -07:00
Matt Guthaus 7c6974dd08 Fix options so it is in /tmp in RAM drive 2018-07-05 16:33:26 -07:00
Matt Guthaus 3260468477 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-07-05 16:27:49 -07:00
Matt Guthaus 077f3f20ec Add return code for regression test 2018-07-05 16:27:47 -07:00
Matt Guthaus cc815f4c33 Fix sense amp spacing after modifying index to be increment by one. 2018-06-29 15:30:17 -07:00
Matt Guthaus 99fe3b87fe Remove temp file. Fixing indexing of sense amp outputs. 2018-06-29 15:22:58 -07:00
Matt Guthaus 6ac24dbf0c Fix module name for python3 2018-06-29 15:12:15 -07:00
Matt Guthaus 3de81c8a67 Close files in trim spice and delay. 2018-06-29 15:11:41 -07:00
Matt Guthaus 8d61ccbc6f Convert byte string to string. 2018-06-29 15:11:14 -07:00
Matt Guthaus 6cd1779f7b Rename pex test so that it ends with _test and will be run by regress.py. 2018-06-29 12:47:22 -07:00
Matt Guthaus 32099646cf Add back fix to revert bitcell from pbitcell. 2018-06-29 12:45:26 -07:00
Matt Guthaus a9849eff3a Merge in mtgrime's fix. 2018-06-29 12:44:26 -07:00
Michael Timothy Grimes 82eeb297dd Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-06-29 12:07:03 -07:00
Michael Timothy Grimes 721f935d66 changing pbitcell tests to revert OPTS.bitcell to bitcell after tests 2018-06-29 12:00:36 -07:00
Matt Guthaus ac7aa4537c Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell. 2018-06-29 11:49:02 -07:00
Matt Guthaus fa17d5e7f3 Change permissions of tests to be executable so you don't have to type python each time. 2018-06-29 11:36:30 -07:00
Matt Guthaus 69921b0844 Add enclosing well to column mux. Move well contact to cell boundary. 2018-06-29 11:35:29 -07:00
Matt Guthaus 3becf92e7c Combine pbitcell tests into one unit test 2018-06-29 10:00:23 -07:00
Matt Guthaus df2dce2439 Fix module import names for python3. Rename parse function to something meaningful. 2018-06-29 09:45:07 -07:00
Matt Guthaus 8cee26bc8c Allow python 3.5. Make easier to revise required version. 2018-06-29 09:23:43 -07:00
Matt Guthaus 2833b706c7 Fix duplicate name check for some modules by checking if name is a substring. Allows pbitcell to pass. 2018-06-29 09:23:23 -07:00
Michael Timothy Grimes d7a024b8fc adding another important port combination to unit tests 2018-06-03 19:36:48 -07:00
Michael Timothy Grimes fea304eac1 corrected gate to contact spacing 2018-05-31 18:31:34 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 9e739d67d4 python 3 changes d.iterkeys() -> iter(d.keys()) 2018-05-29 11:54:10 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes 17769f27c6 small changes to pbitcell 2018-05-22 14:51:42 -07:00
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit 2018-05-22 14:16:51 -07:00
Michael Timothy Grimes 5e4d4bf6cd resolved conflicts with bitcell_array after PrivateRAM merge 2018-05-22 14:12:14 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 58628d7867 Merge branch 'multiport_cleanup' into dev 2018-05-11 09:23:43 -07:00
Matt Guthaus 0e35937da5 Commit local changes. Forgot what the status is. 2018-05-11 09:15:29 -07:00
Matt Guthaus b14bef3bcf Initial merge of incomplete multi-port clean with new supply routing. 2018-05-11 08:18:04 -07:00
Michael Timothy Grimes 3971835f24 changed pbitcell_array tests in regards to addition of read/write ports in pbitcell 2018-05-10 09:40:43 -07:00