 mrg
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27a652ac1b
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Fix bounding box of cap arrays
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2020-11-20 16:54:53 -08:00 |
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mrg
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033111a5f3
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Default to no hierarchical word lines.
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2020-11-19 10:48:35 -08:00 |
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mrg
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86799ae3ff
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Small bug fixes related to new name mapping.
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2020-11-16 13:42:42 -08:00 |
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mrg
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1d729e8f02
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Move pin name mapping to layout class.
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2020-11-16 11:04:03 -08:00 |
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mrg
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93e94e26ec
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Get vdd/gnd from properties if it is defined.
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2020-11-16 10:14:37 -08:00 |
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mrg
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2f994b8c0a
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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mrg
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1624d50ca9
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Fix props bug again.
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2020-11-13 20:35:19 -08:00 |
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mrg
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e9420d57c2
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Fix missing attributes
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2020-11-13 19:04:26 -08:00 |
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mrg
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a2b17a271c
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Port type order generated on the fly
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2020-11-13 16:41:02 -08:00 |
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mrg
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01d191da40
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clk_pin is redundant in DFFs
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2020-11-13 16:23:27 -08:00 |
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mrg
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620e271562
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Fix various typos and errors
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2020-11-13 16:04:07 -08:00 |
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mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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c472a94f1e
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Rework bitcells.
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
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2020-11-13 10:07:40 -08:00 |
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mrg
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bdda7c4f5f
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Add bl/br pins to dummy array
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2020-11-12 12:38:09 -08:00 |
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mrg
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8be1436d51
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Use OPTS.bitcell everywhere
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2020-11-05 16:55:08 -08:00 |
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mrg
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1890385be1
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Use custom cells when needed.
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2020-11-03 11:58:25 -08:00 |
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mrg
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cb3e9517bb
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Use cell_properties to override cell names
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2020-11-03 07:06:01 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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mrg
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857f5cb136
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Fix copy pasta: decoder to predecode
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2020-10-28 15:46:10 -07:00 |
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mrg
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00cb8a28d9
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Fix supply layer query
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2020-10-28 10:36:13 -07:00 |
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mrg
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acfec369d6
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Add ptx cell properties
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2020-10-28 09:54:15 -07:00 |
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mrg
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25495f3d94
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getattr for bank parameters
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2020-10-28 09:21:36 -07:00 |
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mrg
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611a4155b9
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Add initial custom layer properties.
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2020-10-27 15:11:04 -07:00 |
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mrg
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dc991cbcab
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Use pin of pgate to figure out supply layer.
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2020-10-26 15:54:16 -07:00 |
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mrg
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38ba5fc10d
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Use pin of pgate to figure out supply layer.
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2020-10-26 15:53:22 -07:00 |
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mrg
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804814d18d
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Add bitlines to dummy modules
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2020-10-16 13:43:56 -07:00 |
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mrg
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20be7caf98
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Make conditional wl and bl for dummy rows/cols.
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2020-10-15 13:56:37 -07:00 |
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mrg
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6a1f12b62d
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Refactored to utilize OOP
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2020-10-13 11:07:31 -07:00 |
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mrg
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68d74737f7
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Different bitcell and array supply pins
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2020-10-13 07:41:21 -07:00 |
|
 jcirimel
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05667d784f
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move sky130 specific stuff to tech module lib
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2020-10-13 04:48:10 -07:00 |
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mrg
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c3d6be27be
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Fix argument name bug for remove wordlines
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2020-10-08 16:58:38 -07:00 |
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mrg
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8d5db50062
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Fix missing update for left RBL offset
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2020-10-08 16:40:53 -07:00 |
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mrg
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b0b15e8151
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Fix indent bug that failed to create rbl wl pin labels.
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2020-10-08 15:28:01 -07:00 |
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mrg
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01fe02bd90
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Fixes to replica bitline array.
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
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2020-10-08 14:53:44 -07:00 |
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jcirimel
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1e7ae06b7e
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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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2020-10-08 05:32:03 -07:00 |
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jcirimel
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d40c3588ed
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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jcirimel
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4a1a7e637e
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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mrg
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483f6b187c
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RBL driver supply location differs for sky130 and other techs
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2020-10-06 16:47:32 -07:00 |
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mrg
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c2629edc1b
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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jcirimel
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13e2a9f5f7
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fix missed self.left_rbl refactor
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2020-10-06 05:11:15 -07:00 |
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jcirimel
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888646cdf9
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
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8ce23d7f17
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Provide unique WL driver instance name
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2020-10-01 07:17:32 -07:00 |
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Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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f4e6a8895b
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Update riscv unit test
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2020-09-30 08:50:58 -07:00 |
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jcirimel
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7cbf456a4f
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sky130 rba done
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2020-09-30 07:34:05 -07:00 |
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