jcirimel d40c3588ed no wl for col end

2020-10-08 03:34:16 -07:00

..

bank_select.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

bank.py

Allow 16-way column mux

2020-10-06 16:27:02 -07:00

bitcell_array.py

merge in wlbuf and begin work on 32kb memory

2020-10-06 05:03:59 -07:00

bitcell_base_array.py

no wl for col end

2020-10-08 03:34:16 -07:00

col_cap_array.py

Allow replica_bitcell_array without the replica columns for local wordlines.

2020-07-27 16:22:21 -07:00

column_mux_array.py

Rename single_level_column_mux to just column_mux

2020-10-05 08:56:51 -07:00

control_logic.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

custom_cell.py

single port progess

2020-09-14 18:11:38 -07:00

delay_chain.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

dff_array.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

dff_buf_array.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

dff_buf.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

dff_inv_array.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

dff_inv.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

dummy_array.py

no wl for col end

2020-10-08 03:34:16 -07:00

global_bitcell_array.py

Exclude bitcells in other local areas not of interest

2020-09-29 12:15:42 -07:00

hierarchical_decoder.py

merge in dev

2020-10-07 11:54:07 -07:00

hierarchical_predecode2x4.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

hierarchical_predecode3x8.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

hierarchical_predecode4x16.py

Add decoder4x16

2020-10-02 15:52:09 -07:00

hierarchical_predecode.py

merge in dev

2020-10-07 11:54:07 -07:00

local_bitcell_array.py

Provide unique WL driver instance name

2020-10-01 07:17:32 -07:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

orig_bitcell_array.py

single port progess

2020-09-14 18:11:38 -07:00

port_address.py

RBL driver supply location differs for sky130 and other techs

2020-10-06 16:47:32 -07:00

port_data.py

Fix rounding error for wmask with various word_size

2020-09-28 09:53:01 -07:00

precharge_array.py

Update to space according to the bitcell array.

2020-09-14 12:05:45 -07:00

replica_bitcell_array.py

no wl for col end

2020-10-08 03:34:16 -07:00

replica_column.py

no wl for col end

2020-10-08 03:34:16 -07:00

row_cap_array.py

Allow replica_bitcell_array without the replica columns for local wordlines.

2020-07-27 16:22:21 -07:00

sense_amp_array.py

Extend pin correct length in new array.

2020-09-14 12:53:59 -07:00

sense_amp.py

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

tri_gate_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

wordline_buffer_array.py

Create RBL wordline buffer with correct polarity.

2020-09-17 14:45:49 -07:00

wordline_driver_array.py

Create RBL wordline buffer with correct polarity.

2020-09-17 14:45:49 -07:00

write_driver_array.py

Enable riscv tests

2020-09-30 12:39:40 -07:00

write_mask_and_array.py

Fix rounding error for wmask with various word_size

2020-09-28 09:53:01 -07:00