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bank.py
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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bank_select.py
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Change inheritance inits to use super
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2020-08-06 11:33:26 -07:00 |
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bitcell_array.py
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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bitcell_base_array.py
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Fix argument name bug for remove wordlines
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2020-10-08 16:58:38 -07:00 |
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col_cap_array.py
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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column_mux_array.py
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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control_logic.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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custom_cell.py
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single port progess
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2020-09-14 18:11:38 -07:00 |
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delay_chain.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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dff_array.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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dff_buf.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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dff_buf_array.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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dff_inv.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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dff_inv_array.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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dummy_array.py
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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global_bitcell_array.py
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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hierarchical_decoder.py
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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hierarchical_predecode.py
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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hierarchical_predecode2x4.py
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Change inheritance inits to use super
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2020-08-06 11:33:26 -07:00 |
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hierarchical_predecode3x8.py
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Change inheritance inits to use super
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2020-08-06 11:33:26 -07:00 |
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hierarchical_predecode4x16.py
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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local_bitcell_array.py
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Provide unique WL driver instance name
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2020-10-01 07:17:32 -07:00 |
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module_type.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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multibank.py
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Change inheritance inits to use super
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2020-08-06 11:33:26 -07:00 |
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orig_bitcell_array.py
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single port progess
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2020-09-14 18:11:38 -07:00 |
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port_address.py
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RBL driver supply location differs for sky130 and other techs
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2020-10-06 16:47:32 -07:00 |
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port_data.py
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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precharge_array.py
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Update to space according to the bitcell array.
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2020-09-14 12:05:45 -07:00 |
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replica_bitcell_array.py
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Fix missing update for left RBL offset
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2020-10-08 16:40:53 -07:00 |
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replica_column.py
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Fix argument name bug for remove wordlines
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2020-10-08 16:58:38 -07:00 |
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row_cap_array.py
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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sense_amp.py
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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sense_amp_array.py
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Extend pin correct length in new array.
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2020-09-14 12:53:59 -07:00 |
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tri_gate_array.py
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Change inheritance inits to use super
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2020-08-06 11:33:26 -07:00 |
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wordline_buffer_array.py
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Create RBL wordline buffer with correct polarity.
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2020-09-17 14:45:49 -07:00 |
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wordline_driver_array.py
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Create RBL wordline buffer with correct polarity.
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2020-09-17 14:45:49 -07:00 |
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write_driver_array.py
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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write_mask_and_array.py
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
c3d6be27be