 mrg
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62bf713913
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Only remove files at end of openram
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2020-12-01 11:19:37 -08:00 |
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mrg
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0ccb3487b6
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Set default port map
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2020-11-24 13:27:11 -08:00 |
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mrg
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4e10f6d8a6
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Make cell/bitcell custom cell external accessible.
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2020-11-24 12:01:00 -08:00 |
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mrg
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cdcd115cec
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Fix typos
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2020-11-24 10:35:14 -08:00 |
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 jcirimel
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d2bc7340ed
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finish col cap start row cap
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2020-11-24 03:02:55 -08:00 |
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jcirimel
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f40e5f6dba
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start of adding additional granularity to 1port col caps
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2020-11-23 06:55:47 -08:00 |
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mrg
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5ee3f4cc66
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Many edits.
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
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2020-11-22 08:24:47 -08:00 |
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mrg
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95573c858c
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Can redefine number of ports in custom_cell_properties
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2020-11-21 08:05:49 -08:00 |
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 Hunter Nichols
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53e64fb696
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-20 11:16:41 -08:00 |
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mrg
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35c162acbd
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Use internal pin names in path names for signal traces.
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2020-11-19 08:45:09 -08:00 |
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mrg
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fbed738b4a
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Merge multiple cell_name fix.
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2020-11-18 16:27:28 -08:00 |
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mrg
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8c72d3f2e7
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PEP8 and small fix
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2020-11-18 14:01:25 -08:00 |
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mrg
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8507881ea8
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Merge branch 's8_single_port' into dev
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2020-11-18 13:59:43 -08:00 |
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jcirimel
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50a0b88ef8
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fix typo
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2020-11-18 11:02:40 -08:00 |
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jcirimel
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520b496611
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check for cell prop names list
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2020-11-18 10:47:05 -08:00 |
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mrg
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305b546ad5
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PEP8 cleanup
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2020-11-17 16:56:00 -08:00 |
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mrg
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02c1fac3b8
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Remove partial Verilog output
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2020-11-17 16:51:08 -08:00 |
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Hunter Nichols
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ac425643a0
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-17 13:22:56 -08:00 |
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Hunter Nichols
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eaf285639a
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Added debug measurements along main delay paths in SRAM. WIP.
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2020-11-17 12:43:17 -08:00 |
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mrg
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baae28194b
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Add custom cell custom port order code. Update setup/hold to use it.
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2020-11-17 11:12:59 -08:00 |
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mrg
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86799ae3ff
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Small bug fixes related to new name mapping.
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2020-11-16 13:42:42 -08:00 |
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mrg
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1d729e8f02
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Move pin name mapping to layout class.
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2020-11-16 11:04:03 -08:00 |
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mrg
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93e94e26ec
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Get vdd/gnd from properties if it is defined.
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2020-11-16 10:14:37 -08:00 |
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mrg
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e4bc2c4914
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Update property settings with getters/setters
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2020-11-14 08:08:42 -08:00 |
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mrg
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2f994b8c0a
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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mrg
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b4342ac527
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More cleanup
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2020-11-13 17:29:20 -08:00 |
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mrg
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a2b17a271c
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Port type order generated on the fly
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2020-11-13 16:41:02 -08:00 |
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mrg
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01d191da40
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clk_pin is redundant in DFFs
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2020-11-13 16:23:27 -08:00 |
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mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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c472a94f1e
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Rework bitcells.
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
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2020-11-13 10:07:40 -08:00 |
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mrg
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cf63499e76
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Convert bitcells to 1port and 2port
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2020-11-13 08:09:21 -08:00 |
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mrg
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198c0faf85
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Remove special s8 6t names
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2020-11-13 07:45:31 -08:00 |
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mrg
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662d4ea724
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Merge remote-tracking branch 'private/drclvs' into dev
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2020-11-12 16:01:07 -08:00 |
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mrg
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9eeab14639
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Add comment before pininfo
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2020-11-12 14:33:42 -08:00 |
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mrg
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190234df58
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Add PININFO to outputs too
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2020-11-12 12:12:53 -08:00 |
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mrg
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d4c4658c77
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Clean up invalid routing layer error message
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2020-11-12 09:43:08 -08:00 |
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mrg
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d3cb22c8c1
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Fix pin vs module names issue #26
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2020-11-12 09:33:48 -08:00 |
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mrg
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03dad01e4c
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Use readspice to define ports from sp netlist in Magic extract.
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2020-11-10 17:06:24 -08:00 |
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mrg
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66633a843b
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Add PDK layer names to tech file
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2020-11-09 09:10:43 -08:00 |
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mrg
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2c76a2680f
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Adjust openram options.
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
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2020-11-05 13:12:26 -08:00 |
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|
Matt Guthaus
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844b850b74
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Fix typo in 1w_1r bitcell
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2020-11-03 17:14:45 -08:00 |
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mrg
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1de545fc8e
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Fix row and col cap custom names by adding default.
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2020-11-03 13:32:15 -08:00 |
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mrg
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29ac541b28
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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mrg
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1890385be1
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Use custom cells when needed.
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2020-11-03 11:58:25 -08:00 |
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mrg
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cb3e9517bb
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Use cell_properties to override cell names
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2020-11-03 07:06:01 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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f9787eb878
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Use bitcell_base for all bitcells. Fix missing setup_bitcell call
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2020-11-02 17:00:15 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
|
 Tim 'mithro' Ansell
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95d77119c7
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Add caches to GDS related functions in utils.py
* Cache the GDS reader.
* Cache the properties (size / pins / etc) measured from the GDS files.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
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2020-11-02 09:52:00 -08:00 |
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mrg
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f6c5f48b4c
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Default channel route is true
|
2020-10-28 10:31:05 -07:00 |
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